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參數(shù)資料
| 型號： | LS7212-S |
| 英文描述： | Delay Line |
| 中文描述： | 延遲線 |
| 文件頁數(shù)： | 8/8頁 |
| 文件大?。?/td> | 66K |
| 代理商： | LS7212-S |
FIGURE 10. PROGRAMMABLE FREQUENCY DIVIDER
17
10
11
12
13
14
15
16
18
WB0
WB1
WB2
WB3
WB4
WB5
WB6
WB7
1
2
4
A
B
TRIG
7
RESET
8
9
OUT
Vss
o
+V
i
+V
3
LS7212
i
o
Case 1, Mode = DO;
÷
4
o
Case 2, Mode = DD;
÷
6
CASE 1. MODE = DO or DR; PRESCALE FACTOR, S = 1
In this setup a frequency division of the input clock, i by a factor of 2 to 257, in increments of 1 can be
obtained according to the equation:
o =
where W (weighting factor) = 0 to 255
i
W + 2
The o pulse width is non-symmetrical (non-50% duty -cycle)
CASE 2. MODE = DD; PRESCALE FACTOR, S = 1
In this setup a frequency division of the input clock, i by a factor of 2 to 512, in increments of 2 can be
obtained according to the equation:
o
=
where W (weighting factor) = 0 to 255
i
2(W + 1)
The o pulse widths are symmetrical with 50% duty -cycle
EXAMPLES OF CASE 1 and CASE 2 FREQUENCY DIVISIONS WITH W = 2
V
DD
CLOCK
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