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參數(shù)資料
| 型號(hào)： | LS7211-S |
| 英文描述： | Delay Line |
| 中文描述： | 延遲線 |
| 文件頁(yè)數(shù)： | 5/8頁(yè) |
| 文件大?。?/td> | 66K |
| 代理商： | LS7211-S |
t
1
t
2
t
3
A = 0, B = 1, Delayed Operate
Programmed Delay
Immediat e Release
t
4
t
1
t
4
Clock
TRIG
A,B
WB0-WB7
OUT
t
0
A
B
D
C
E
F
G
H
OUT(DD)
OUT(DR)
OUT(DO)
OUT(OS)
RESET
TRIG
Note 1.
TRIG input is clocked in by the negative edge of external clock.
Note 2.
Inputs A, B and WB0 - WB7 are sampled only at a TRIG input transition and ignored at all other times.
Note 3.
OUT is switched by the positive edge of the external clock.
FIGURE 3. INPUT/OUTPUT TIMING
A.
Turn-on delay in DO and DD modes; Pulse-width in OS mode.
B.
Turn-off delay in DR and DD modes.
C.
Pulse-width extended by re-trigger in OS mode. No effect in DO and DD modes because TRIG switches back low
before turn-on delay has timed out.
D.
Turn-off delay in DR mode.
E.
Turn-on delay in DO and DD modes; pulse-width in OS mode.
F.
No effect in DO, DR and DD modes because of TRIG’s switching back to opposite levels.
G.
Time-outs aborted and OUT force high by RESET.
H.
After the removal of RESET, OUT switches to the inverse polarity of TRIG immediately (DR) or after the timeout
(DO,DD). No effect in OS.
FIGURE 4. MODE ILLUSTRATION WITH TRIG, OUT AND RESET
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| LS7212-S | Delay Line |
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| LSA1501 | ASIC |
| LSA1502 | ASIC |
| LSA1503 | ASIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LS7212 | 制造商:LSI 制造商全稱:LSI 功能描述:PROGRAMMABLE DIGITAL DELAY TIMER |
| LS7212N | 制造商:LSI 制造商全稱:LSI 功能描述:PROGRAMMABLE DIGITAL DELAY TIMER |
| LS7212-S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Delay Line |
| LS7213 | 制造商:LSI 制造商全稱:LSI 功能描述:PROGRAMMABLE DIGITAL DELAY TIMER |
| LS7213R | 制造商:LSI 制造商全稱:LSI 功能描述:PROGRAMMABLE DIGITAL DELAY TIMER |
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