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參數(shù)資料
| 型號(hào)： | LR38620 |
| 廠商： | Sharp Corporation |
| 英文描述： | Timing Generator IC for 4200 k-pixwl CCD |
| 中文描述： | 時(shí)序發(fā)生器芯片CCD的4200的K - pixwl |
| 文件頁數(shù)： | 4/9頁 |
| 文件大?。?/td> | 95K |
| 代理商： | LR38620 |
LR38620
4
PIN NO.
SYMBOL
IO SYMBOL
POLARITY
PIN NAME
DESCRIPTION
16
BCPX
O3MR1
Optical black clamp
pulse output
A pulse to clamp the optical black signal.
This pulse is controlled by serial data BCPCNT.
BCPCNT = H; This pulse stays high during the
absence of effective pixels within the
vertical blanking or during the
sweepout signal.
BCPCNT = L; This pulse stays high during the
sweepout signal.
A pulse to clamp the dummy outputs of the CCD signal.
This pulse stays high during the sweepout period.
An output pin for AD converter. The output phase of
ADCK is selected by serial data in 90 steps.
A pulse to clamp the feed-through level for the CCD.
The output phase and output polarity of FCDS are
selected by serial data.
A pulse to sample-hold the signal for the CCD.
The output phase and output polarity of FS are selected
by serial data.
A trigger pulse for effective signal period.
The pulse is used in the color separator.
The signal switches between high and low at every line.
Supply of +3.3 V power.
Supply of +3.3 V power.
A grounding pin.
An input pin for reference clock oscillation.
The frequency is 49.0909 MHz.
An output pin for reference oscillation.
The output is the inverse of CKI (pin 26).
An output pin to generate HD and VD pulses.
The frequency is 24.54545 MHz.
An output pin for DSP IC. The frequency is 24.54545 MHz.
The output phase of DCLK is selected by serial data in
90 steps.
An input pin for reference of vertical pulse.
Connect to VD pin of DSP IC.
An input pin for reference of horizontal pulse.
Connect to HD pin of DSP IC.
An input pin for the strobe pulse, to control the functions
of LR38620. For details, see "
Serial Data Control
".
An input pin for the clock of the shift register, to control
the functions of LR38620. For details, see "
Serial Data
Control
".
Clamp pulse output
O3MR1
CLPX
17
18
ADCK
O6M32
AD clock output
CDS pulse output 1
O6M32
FCDS
19
20
FS
O6M32
CDS pulse output 2
Trigger output
Line index pulse
output
Power supply
Power supply
Ground
O3MR1
SHTR
21
22
ID
O3MR1
–
–
–
V
DD3
V
DD3
GND
23
24
25
–
–
–
–
26
CKI
OSCI3
Clock input
Clock output
OSCO3
CKO
27
–
Clock output
O6M32
CLK
28
29
DCLK
O6M32
Clock output
Vertical reference
pulse input
Horizontal drive
pulse input
IC3
VD
30
31
HD
IC3
Strobe pulse input
ICSD3
ED
0
32
–
–
33
ED
1
ICSD3
Shift register clock
input
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