LR38516
4
PIN NO.
SYMBOL
I/O
POLARITY
PIN NAME
DESCRIPTION
A pulse to sample-hold the signal from CCD.
The polarity can be changed by serial data.
The output phase of FS is selected by serial data.
Supply of +5 V power.
A pulse to sample-hold the signal from CDS circuit.
The polarity can be changed by serial data.
The output phase of RS is selected by serial data.
A pulse to reset the charge of output circuit.
Connect to
R
pin of CCD through the DC offset circuit.
The output phase of FR is selected by serial data.
CDS pulse output 2
O6MA5
FS
19
20
V
DD5
–
Power supply
S/H pulse output
O6MA5
RS
21
–
–
A grounding pin.
A test pin. Set open or to L level in the normal mode.
An input pin for reference clock oscillation.
Connect to CKO (pin 26) with R.
Frequency : 24.54545 MHz (1 560 fH)
Ground
Test pin 2
–
GND
TST
2
23
24
22
FR
O6MA52
Reset pulse output
ICD3
fH = Horizontal frequency
Clock input
OSCI3
CKI
25
–
–
26
CKO
OSCO3
Clock output
An output pin for reference clock oscillation.
The output is the inverse of CKI (pin 25).
An output pin to generate HD and VD pulses.
Connect to clock input pin of SSG IC.
Frequency : 12.27273 MHz (780 fH)
An output pin for DSP IC. The output phase of DCLK is
selected by serial data step by 90.
Frequency : 12.27273 MHz (780 fH)
An input pin for reference of vertical pulse.
Connect to VD pin of DSP IC.
Supply of +3 V power.
A grounding pin.
An input pin for reference of horizontal pulse.
Connect to HD pin of DSP IC.
An input pin for the strobe pulse, to control the functions
of LR38516. For details, see
"
Serial Data Control
"
.
An input pin for the clock of the shift register, to control
the functions of LR38516. For details, see
"
Serial Data
Control
"
.
18
FCDS
O6MA5
CDS pulse output 1
A pulse to clamp the feed-through level from CCD.
The polarity can be changed by serial data.
The output phase of FCDS is selected by serial data.
–
Clock output
O6MA3
CLK
27
An input pin for the data of the shift register, to control
the functions of LR38516. For details, see
"
Serial Data
Control
"
.
A test pin. Set open or to L level in the normal mode.
Shift register data
input
ED
2
35
IC3
–
Clock output
O6MA3
DCLK
28
Vertical reference
pulse input
Power supply
Ground
Horizontal reference
pulse input
IC3
DMVD
29
–
–
30
31
V
DD3
GND
–
–
32
HD
IC3
Strobe pulse input
ED
0
33
IC3
–
–
IC3
34
ED
1
Shift register clock
input
–
ICD3
36
TST
3
Test pin 3