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參數(shù)資料
| 型號(hào)： | LR38269 |
| 廠商： | Sharp Corporation |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | Digital Signal Processor for Color CCD Cameras |
| 中文描述： | 數(shù)字信號(hào)處理器的彩色CCD相機(jī) |
| 文件頁(yè)數(shù)： | 11/20頁(yè) |
| 文件大?。?/td> | 93K |
| 代理商： | LR38269 |
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LR38269
11
ADDRESS
69h
6Ah
6Bh
6Ch
BIT
6-0
4-0
6-0
7
6-1
CONTENTS
NAME
APT_HCL
APT_VGA
APT_VCL
CBLK_LV
SETUP
6Fh
TG_SEL1
7-5
4-2
ADCK phase setting (6 steps per 60)
FS phase setting (±2 ns x 3)
70h
TG_SEL2
7-5
4-2
FCDS phase setting (±2 ns x 3)
FR phase setting (±2 ns x 3)
71h
ENC_MUTE
SYNC_SW
SEL_RB
OUT_GAIN
7
6
5
Encoder muting
SYNC adder
Serial digital data setting
Gain of video output amplifier
0 : OFF
0 : ON
1 : ON
1 : OFF
72h
73h
74h
75h
SYNC_LEV
BAS_R
BAS_B
7-0
7-0
7-0
7
6-0
SYNC level (80h = 40 IRE)
BURST level of R – Y
BURST level of B – Y
Muting at power-on
Muting period (data multiplied by 1 field period)
MUTE_OUT
76h
77h
TEST
VRI
TEST
TEST
2-0
2
1
0
Test data (EEPROM data must be 00h)
EXCKI pin function
Test data (EEPROM data must be 0)
Test data (EEPROM data must be 0)
1 : VRI function
0 : Clock input
78h
KEI_AGC
8
AGC gain to set KEI-PULSE high
(NOTE 1)
ADDRESS
01
Bit 2
1
0
x
1
0
1
0
SIGNAL OUTPUT
HD (Pin 60)
HD
HD
HD
HD
HD
BELL
BELL
VD (Pin 61)
VD for video out
VD for CCD driving
CSYNC
VD for video out
VD for CCD driving
VD for video out
VD for CCD driving
DCK
1
(Pin 47)
DCK
1
DCK
1
DCK
1
CSYNC
CSYNC
CSYNC
CSYNC
Bit 0
0
0
1
0
0
1
1
Bit 3
DIGITAL
1
ANALOG
0
Horizontal aperture signal coring
Vertical aperture gain
Vertical aperture signal coring
CBLK level selection
Set up level
0 : 00h
1 : 10h
6Dh
6Eh
VARI_Y
4-0
luminance signal position
The following setting is available under both EEPSL = H and digital output mode
WB1 (LSB), WB2, BACK, EEMDS, EEMD1 EEMD2, EEMD3, MIR (MSB)
SW_CTRL
7-0
4-0
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