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參數(shù)資料
| 型號： | LPR521KMB24 |
| 廠商： | LOGIC DEVICES INC |
| 元件分類： | 數(shù)字信號處理外設 |
| 英文描述： | 16-BIT, DSP-PIPELINE REGISTER, CQCC44 |
| 封裝： | CERAMIC, LCC-44 |
| 文件頁數(shù)： | 1/6頁 |
| 文件大?。?/td> | 132K |
| 代理商： | LPR521KMB24 |
DEVICES INCORPORATED
LPR520/521
4 x 16-bit Multilevel Pipeline Register
LPR520/521
4 x 16-bit Multilevel Pipeline Register
Pipeline Registers
06/30/95–LDS.P520/1-K
1
K
Four 16-bit Registers
K
Implements Double 2-Stage Pipe-
line or Single 4-Stage Pipeline
Register
K
Hold, Shift, and Load Instructions
K
Separate Data In and Data Out Pins
K
High-Speed, Low Power CMOS
Technology
K
Three-State Outputs
K
DESC SMD No. 5962-89716
K
Available 100% Screened to
MIL-STD-883, Class B
K
Package Styles Available:
40-pin Plastic DIP
40-pin Ceramic DIP
44-pin Plastic LCC, J-Lead
44-pin Ceramic LCC
FEATURES
DESCRIPTION
DEVICES INCORPORATED
The
LPR520
and
LPR521
are functionally
compatible with the IDT29FCT520/
IDT29FCT521 and AMD Am29520/
Am29521 but have 16-bit inputs and
outputs. They are implemented in low
power CMOS.
The LPR520 and LPR521 contain four
registers which can be configured as
two independent, 2-level pipelines or
as one 4-level pipeline.
The Instruction pins, I
1-0
, control the
loading of the registers. For either
device, the registers may be config-
ured as a four-stage delay line, with
data loaded into R1 and shifted
sequentially through R2, R3, and R4.
Also, for the LPR520, data may be
loaded from the inputs into either R1
or R3 with only R2 or R4 shifting. The
LPR521 differs from the LPR520 in
that R2 and R4 remain unchanged
during this type of data load, as
shown in Tables 1 and 2. Finally, I
1-0
may be set to prevent any register
from changing.
The S
1-0
select lines control a 4-to-1
multiplexer which routes the contents
of any of the registers to the Y output
pins. The independence of the I and S
controls allows simultaneous write
and read operations on different
registers.
S
1
S
0
Register Selected
L
L
Register 4
L
H
Register 3
H
L
Register 2
H
H
Register 1
T
ABLE
3.
O
UTPUT
S
ELECT
I
1
I
0
Description
L
L
D
R1
R1
R2
R2
R3
R3
R4
L
H
HOLD
HOLD
D
R3
HOLD
H
L
D
R1
HOLD
HOLD
HOLD
H
H
ALL REGISTERS ON HOLD
T
ABLE
2.
LPR521 I
NSTRUCTION
T
ABLE
I
1
I
0
Description
L
L
D
R1
R1
R2
R2
R3
R3
R4
L
H
HOLD
HOLD
D
R3
R3
R4
H
L
D
R1
R1
R2
HOLD
HOLD
H
H
ALL REGISTERS ON HOLD
T
ABLE
1.
LPR520 I
NSTRUCTION
T
ABLE
LPR520/521 B
LOCK
D
IAGRAM
M
REG 1
REG 2
REG 3
REG 4
R
R
R
R
M
D
15-0
16
16
OE
Y
15-0
S
1-0
I
1-0
CLK
2
2
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相關代理商/技術參數(shù) |
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| LPR521KMB30 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Pipeline Register |
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| LPR521KME30 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Pipeline Register |
| LPR521PC15 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Pipeline Register |
| LPR521PC22 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Pipeline Register |
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