- 您現(xiàn)在的位置：買(mǎi)賣IC網(wǎng) > PDF目錄378651 > LPR520 (Logic Devices Incorporated) 4 x 16-bit Multilevel Pipeline Register PDF資料下載
參數(shù)資料
| 型號(hào)： | LPR520 |
| 廠商： | Logic Devices Incorporated |
| 英文描述： | 4 x 16-bit Multilevel Pipeline Register |
| 中文描述： | 4 × 16位多級(jí)管道注冊(cè) |
| 文件頁(yè)數(shù)： | 1/5頁(yè) |
| 文件大?。?/td> | 162K |
| 代理商： | LPR520 |
DEVICES INCORPORATED
LPR520
4 x 16-bit Multilevel Pipeline Register
4 x 16-bit Multilevel Pipeline Register
Pipeline Registers
08/02/2000–LDS.P520-C
1
K
Four 16-bit Registers
K
Implements Double 2-Stage
Pipeline or Single 4-Stage Pipeline
Register
K
Hold, Shift, and Load Instructions
K
Separate Data In and Data Out Pins
K
High-Speed, Low Power CMOS
Technology
K
Three-State Outputs
K
44-pin PLCC, J-Lead
FEATURES
DESCRIPTION
DEVICES INCORPORATED
The
LPR520
is functionally compat-
ible with the L29C520 but have 16-bit
inputs and outputs. The LPR520 is
implemented in low power CMOS.
The LPR520 contains four registers
which can be configured as two
independent, 2-level pipelines or as
one 4-level pipeline.
The Instruction pins, I
1-0
, control the
loading of the registers. The registers
may be configured as a four-stage
delay line, with data loaded into R1
and shifted sequentially through R2,
R3, and R4. Also, data may be loaded
from the inputs into either R1 or R3
with only R2 or R4 shifting. Finally,
I
1-0
may be set to prevent any register
from changing.
The S
1-0
select lines control a 4-to-1
multiplexer which routes the contents
of any of the registers to the Y output
pins. The independence of the I and S
controls allows simultaneous write
and read operations on different
registers.
S
1
S
0
Register Selected
L
L
Register 4
L
H
Register 3
H
L
Register 2
H
H
Register 1
T
ABLE
2.
O
UTPUT
S
ELECT
I
1
I
0
Description
L
L
D
R1
R1
R2
R2
R3
R3
R4
L
H
HOLD
HOLD
D
R3
R3
R4
H
L
D
R1
R1
R2
HOLD
HOLD
H
H
ALL REGISTERS ON HOLD
T
ABLE
1.
LPR520 I
NSTRUCTION
T
ABLE
LPR520 B
LOCK
D
IAGRAM
M
REG 1
REG 2
REG 3
REG 4
R
R
R
R
M
D
15-0
16
16
OE
Y
15-0
S
1-0
I
1-0
CLK
2
2
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LPR520JC22 | 4 x 16-bit Multilevel Pipeline Register |
| LPS-75 | CHOKE,AXIAL,MOLDED RF,4.7uH, 10% INDUCTIVE TOL,380 IDC |
| LPS-75-12 | CHOKE,AXIAL,MOLDED RF,47uH, 10% INDUCTIVE TOL,195 IDC |
| LPS-75-15 | CHOKE,AXIAL,MOLDED RF,470uH, 10% INDUCTIVE TOL,92 IDC |
| LPS-75-24 | OUSING,4 POS,640622-4-VP, .100",BLU,NYLON,26AWG,F/T,(10) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LPR520CC15 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Pipeline Register |
| LPR520CC22 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Pipeline Register |
| LPR520CC25 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Pipeline Register |
| LPR520CM18 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Pipeline Register |
| LPR520CM24 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Pipeline Register |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。