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| 型號(hào)： | LPC47U32X |
| 英文描述： | Peripheral (Multifunction) Controller |
| 中文描述： | 周邊（多功能）控制器 |
| 文件頁(yè)數(shù)： | 97/228頁(yè) |
| 文件大小： | 1269K |
| 代理商： | LPC47U32X |
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SMSC DS – LPC47M192
Page 97
Rev. 03/30/05
DATASHEET
a) When serviceIntr is 0, dmaEn is 0, direction is 0 and there are writeIntrThreshold or more free bytes in the
FIFO. Also, an interrupt is generated when serviceIntr is cleared to 0 whenever there are writeIntrThreshold
or more free bytes in the FIFO.
b) When serviceIntr is 0, dmaEn is 0, direction is 1 and there are readIntrThreshold or more bytes in the FIFO.
Also, an interrupt is generated when serviceIntr is cleared to 0 whenever there are readIntrThreshold or
more bytes in the FIFO.
3) When nErrIntrEn is 0 and nFault transitions from high to low or when nErrIntrEn is set from 1 to 0 and nFault is
asserted.
4) When ackIntEn is 1 and the nAck signal transitions from a low to a high.
FIFO Operation
The FIFO threshold is set in the chip configuration registers. All data transfers to or from the parallel port can
proceed in DMA or Programmed I/O (non-DMA) mode as indicated by the selected mode. The FIFO is used by
selecting the Parallel Port FIFO mode or ECP Parallel Port Mode. (FIFO test mode will be addressed separately.)
After a reset, the FIFO is disabled. Each data byte is transferred by a Programmed I/O cycle or DMA cycle
depending on the selection of DMA or Programmed I/O mode.
The following paragraphs detail the operation of the FIFO flow control. In these descriptions, <threshold> ranges
from 1 to 16. The parameter FIFOTHR, which the user programs, is one less and ranges from 0 to 15.
A low threshold value (i.e. 2) results in longer periods of time between service requests, but requires faster servicing
of the request for both read and write cases. The host must be very responsive to the service request. This is the
desired case for use with a “fast” system. A high value of threshold (i.e. 12) is used with a “sluggish” system by
affording a long latency period after a service request, but results in more frequent service requests.
DMA TRANSFERS
DMA transfers are always to or from the ecpDFifo, tFifo or CFifo. DMA utilizes the standard PC DMA services. To
use the DMA transfers, the host first sets up the direction and state as in the programmed I/O case. Then it programs
the DMA controller in the host with the desired count and memory address. Lastly it sets dmaEn to 1 and serviceIntr
to 0. The ECP requests DMA transfers from the host by encoding the LDRQ# pin. The DMA will empty or fill the
FIFO using the appropriate direction and mode. When the terminal count in the DMA controller is reached, an
interrupt is generated and serviceIntr is asserted, disabling DMA. In order to prevent possible blocking of refresh
requests a DMA cycle shall not be requested for more than 32 DMA cycles in a row. The FIFO is enabled directly by
the host initiating a DMA cycle for the requested channel, and addresses need not be valid. An interrupt is generated
when a TC cycle is received. (Note: The only way to properly terminate DMA transfers is with a TC cycle.)
DMA may be disabled in the middle of a transfer by first disabling the host DMA controller. Then setting serviceIntr to
1, followed by setting dmaEn to 0, and waiting for the FIFO to become empty or full. Restarting the DMA is
accomplished by enabling DMA in the host, setting dmaEn to 1, followed by setting serviceIntr to 0.
DMA Mode - Transfers from the FIFO to the Host
(Note: In the reverse mode, the peripheral may not continue to fill the FIFO if it runs out of data to transfer, even if the
chip continues to request more data from the peripheral.)
The ECP requests a DMA cycle whenever there is data in the FIFO. The DMA controller must respond to the request
by reading data from the FIFO. The ECP stops requesting DMA cycles when the FIFO becomes empty or when a TC
cycle is received, indicating that no more data is required. If the ECP stops requesting DMA cycles due to the FIFO
going empty, then a DMA cycle is requested again as soon as there is one byte in the FIFO. If the ECP stops
requesting DMA cycles due to the TC cycle, then a DMA cycle is requested again when there is one byte in the FIFO,
and serviceIntr has been re-enabled.
Programmed I/O Mode or Non-DMA Mode
The ECP or parallel port FIFOs may also be operated using interrupt driven programmed I/O. Software can determine
the writeIntrThreshold, readIntrThreshold, and FIFO depth by accessing the FIFO in Test Mode.
Programmed I/O transfers are to the ecpDFifo at 400H and ecpAFifo at 000H or from the ecpDFifo located at 400H,
or to/from the tFifo at 400H. To use the programmed I/O transfers, the host first sets up the direction and state, sets
dmaEn to 0 and serviceIntr to 0.
The ECP requests programmed I/O transfers from the host by activating the interrupt. The programmed I/O will empty
or fill the FIFO using the appropriate direction and mode.
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