- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄358934 > LPC47N267-MN (STANDARD MICROSYSTEMS CORP) 100 Pin LPC Notebook I/O with X-Bus Interface PDF資料下載
參數(shù)資料
| 型號(hào)： | LPC47N267-MN |
| 廠商： | STANDARD MICROSYSTEMS CORP |
| 元件分類(lèi)： | 外設(shè)及接口 |
| 英文描述： | 100 Pin LPC Notebook I/O with X-Bus Interface |
| 中文描述： | MULTIFUNCTION PERIPHERAL, PQFP100 |
| 封裝： | 12 X 12 MM, 1.40 MM HEIGHT, STQFP-100 |
| 文件頁(yè)數(shù)： | 107/228頁(yè) |
| 文件大?。?/td> | 1269K |
| 代理商： | LPC47N267-MN |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)當(dāng)前第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)第199頁(yè)第200頁(yè)第201頁(yè)第202頁(yè)第203頁(yè)第204頁(yè)第205頁(yè)第206頁(yè)第207頁(yè)第208頁(yè)第209頁(yè)第210頁(yè)第211頁(yè)第212頁(yè)第213頁(yè)第214頁(yè)第215頁(yè)第216頁(yè)第217頁(yè)第218頁(yè)第219頁(yè)第220頁(yè)第221頁(yè)第222頁(yè)第223頁(yè)第224頁(yè)第225頁(yè)第226頁(yè)第227頁(yè)第228頁(yè)
KIRQ
If “EN FLAGS” has been executed and P24 is set to a one: the OBF flag is gated onto KIRQ. The KIRQ signal can be
connected to system interrupt to signify that the LPC47M192 CPU has written to the output data register via “OUT
DBB,A”. If P24 is set to a zero, KIRQ is forced low. On power-up, after a valid RST pulse has been delivered to the
device, KIRQ is reset to 0. KIRQ will normally reflects the status of writes “DBB”. (KIRQ is normally selected as IRQ1
for keyboard support.)
If “EN FLAGS” has not been executed: KIRQ can be controlled by writing to P24. Writing a zero to P24 forces KIRQ
low; a high forces KIRQ high.
SMSC DS – LPC47M192
Page 107
Rev. 03/30/05
DATASHEET
MIRQ
If “EN FLAGS” has been executed and P25 is set to a one:; IBF is inverted and gated onto MIRQ. The MIRQ signal
can be connected to system interrupt to signify that the LPC47M192 CPU has read the DBB register. If “EN FLAGS”
has not been executed, MIRQ is controlled by P25, Writing a zero to P25 forces MIRQ low, a high forces MIRQ high.
(MIRQ is normally selected as IRQ12 for mouse support).
Gate A20
A general purpose P21 is used as a software controlled Gate A20 or user defined output.
8042 PINS
The 8042 functions P17, P16 and P12 are implemented as in a true 8042 part. Reference the 8042 spec for all
timing. A port signal of 0 drives the output to 0. A port signal of 1 causes the port enable signal to drive the output to
1 within 20-30nsec. After 500nsec (six 8042 clocks) the port enable goes away and the external pull-up maintains
the output signal as 1.
In 8042 mode, the pins can be programmed as open drain. When programmed in open drain mode, the port enables
do not come into play. If the port signal is 0 the output will be 0. If the port signal is 1, the output tristates: an external
pull-up can pull the pin high, and the pin can be shared. In 8042 mode, the pins cannot be programmed as input nor
inverted through the GP configuration registers.
7.11.2 EXTERNAL KEYBOARD AND MOUSE INTERFACE
Industry-standard PC-AT-compatible keyboards employ a two-wire, bidirectional TTL interface for data transmission.
Several sources also supply PS/2 mouse products that employ the same type of interface. To facilitate system
expansion, the LPC47M192 provides four signal pins that may be used to implement this interface directly for an
external keyboard and mouse.
The LPC47M192 has four high-drive, open-drain output, bidirectional port pins that can be used for external serial
interfaces, such as external keyboard and PS/2-type mouse interfaces. They are KCLK, KDAT, MCLK, and MDAT.
P26 is inverted and output as KCLK. The KCLK pin is connected to TEST0. P27 is inverted and output as KDAT.
The KDAT pin is connected to P10. P23 is inverted and output as MCLK. The MCLK pin is connected to TEST1.
P22 is inverted and output as MDAT. The MDAT pin is connected to P11.
Note
: External pull-ups may be required.
7.11.3 KEYBOARD POWER MANAGEMENT
The keyboard provides support for two power-saving modes: soft powerdown mode and hard powerdown mode. In
soft powerdown mode, the clock to the ALU is stopped but the timer/counter and interrupts are still active. In hard
power down mode the clock to the 8042 is stopped.
Soft Power Down Mode
This mode is entered by executing a HALT instruction. The execution of program code is halted until either RESET is
driven active or a data byte is written to the DBBIN register by a master CPU. If this mode is exited using the
interrupt, and the IBF interrupt is enabled, then program execution resumes with a CALL to the interrupt routine,
otherwise the next instruction is executed. If it is exited using RESET then a normal reset sequence is initiated and
program execution starts from program memory location 0.
Hard Power Down Mode
This mode is entered by executing a STOP instruction. The oscillator is stopped by disabling the oscillator driver
cell. When either RESET is driven active or a data byte is written to the DBBIN register by a master CPU, this mode
will be exited (as above). However, as the oscillator cell will require an initialization time, either RESET must be held
active for sufficient time to allow the oscillator to stabilize. Program execution will resume as above.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LPC47N227-MN | 100 Pin Super I/O with LPC Interface for Notebook Applications |
| LPC47N227TQFP | 100 Pin Super I/O with LPC Interface for Notebook Applications |
| LPC47M182-NR | ADVANCED I/O CONTROLLER WITH MOTHERBOARD GLUE LOGIC |
| LPC47M182-NW | ADVANCED I/O CONTROLLER WITH MOTHERBOARD GLUE LOGIC |
| LPC47M192-NC | LPC SUPER I/O WITH HARDWARE MONITORING BLOCK |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LPC47N267-MV | 功能描述:輸入/輸出控制器接口集成電路 Notebk I/O Contrllr RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| LPC47N350 | 制造商:SMSC 制造商全稱(chēng):SMSC 功能描述:LEGACY FREE KEYBOARD EMBEDDED CONTROLLER WITH SPI AND LPC DOCKING INTERFACE |
| LPC47N350-NC | 功能描述:輸入/輸出控制器接口集成電路 Advncd I/O Contrllr RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| LPC47N350-NU | 功能描述:輸入/輸出控制器接口集成電路 Advanced I/O Controller RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| LPC47N354-AAQ | 制造商:SMSC 功能描述: |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。