To put the chip in the first XNOR chain test mode, tie LAD0 (pin 20) and LFRAME# (pin 24) low. Then toggle
PCI_RESET# (pin 26) from a low to a high state. Once the chip is put into XNOR chain test mode, LAD0 (pin 20) and
LFRAME# (pin 24) become part of the chain.
To exit the first XNOR chain test mode tie LAD0 (pin 20) or LFRAME# (pin 24) high. Then toggle PCI_RESET# (pin
26) from a low to a high state. A VCC POR will also cause the XNOR chain test mode to be exited. To verify the test
mode has been exited, observe the output at TXD1 (pin 85). Toggling any of the input pins in the chain should not
cause its state to change.
SMSC DS – LPC47M192
Page 224
Rev. 03/30/05
DATASHEET
Setup of Super I/O XNOR Chain
Warning:
Ensure power supply is off during setup.
1. Connect VSS (pins 7, 31, 60, & 76) and AVSS (pin 40) to ground.
2. Connect VCC (pins 53, 65, & 93), VTR (pin 18), and VREF (pin 44) to VCC (3.3V).
3. Connect an oscilloscope or voltmeter to TXD1 (pin 85).
4. All other pins should be tied to ground.
Testing
1. Turn power on.
2. With LAD0 (pin 20) and LFRAME# (pin 24), low, bring PCI_RESET# (pin 26) high. The chip is now in XNOR
chain test mode. At this point, all inputs to the first XNOR chain are low. The output, on TXD1 (pin 85),
should also be low. Refer to INITIAL CONFIG on TRUTH TABLE 1.
3. Bring pin 100 high. The output on TXD1 (pin 85) should go high. Refer to STEP ONE on TRUTH TABLE 1.
4. In descending pin order, bring each input high. The output should switch states each time an input is
toggled. Continue until all inputs are high. The output on TXD1 should now be low. Refer to END CONFIG
on TRUTH TABLE 1.
5. The current state of the chip is now represented by INITIAL CONFIG in TRUTH TABLE 2.
6. Each input should now be brought low, starting at pin one and continuing in ascending order. Continue until
all inputs are low. The output on TXD1 should now be low. Refer to TRUTH TABLE 2.
7. To exit test mode, tie LAD0 (pin 20) OR LFRAME# (pin 24) high, and toggle PCI_RESET# from a low to a
high state.
TRUTH TABLE 1 - Toggling Inputs in Descending Order
PIN
100
L
H
H
H
H
H
…
H
H
PIN
99
L
L
H
H
H
H
…
H
H
PIN
98
L
L
L
H
H
H
…
H
H
PIN
97
L
L
L
L
H
H
…
H
H
PIN 96
L
L
L
L
L
H
…
H
H
PIN ...
L
L
L
L
L
L
…
H
H
PIN 1
L
L
L
L
L
L
…
L
H
OUTPUT
PIN 85
L
H
L
H
L
H
…
H
L
INITIAL CONFIG
STEP 1
STEP 2
STEP 3
STEP 4
STEP 5
…
STEP N
END CONFIG