
SMSC DS – LPC47M14X
Page 205
Rev. 03/19/2001
14 LPC47M14X REVISIONS
PAGE(S)
1
3
10
SECTION/FIGURE/ENTRY
Features
General Description
DESCRIPTION OF PIN FUNCTIONS
CORRECTION
See italicized text
See italicized text
Changes to Note 4 (see
italicized text)
See italicized text
See the “Low Pin Count
(LPC) Interface
Specification” Revision
1.0 (See italicized text)
See italicized text
Reserved, read ‘0’.
This part does not
support non-DMA
mode.
This part does not
support non-DMA
mode.
Non-DMA Mode Flag -
Write ‘0’. This part does
not support non-DMA
mode.
Note added (see
italicized text)
(see italicized text)
The divisor for each fan
is programmable via
the Fan Control
Register, which is
located in the Runtime
Register block at offset
0xFA.
Changes to Note 5 (see
italicized text)
Changes to Note 6 (see
italicized text)
0x22 R/W Address - 0:
Power Off or Disabled
1: Power On or
Enabled
0x23 R/W Address -
(see Note in the “FDC
Power Management”
section.)
KRST_GA20 - Bits[6:5]
reset on VTR POR only
Values added to:
V
CC
Supply Current
Active, V
TR
Supply
Current Active and V
REF
Supply Current Active
Note added (see
italicized text)
DATE
REVISED
03/19/01
03/19/01
03/19/01
21
22
Field Definitions
I/O Read and Write Cycles, DMA Read and
Write Cycles, CLOCKRUN Protocol, LPCPD
Protocol, SYNC Protocol
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34
I/O Transfers
Bit 5 Non-DMA
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40
Non-DMA Mode - Transfers from the FIFO to
the Host, Non-DMA Mode - Transfers from the
Host to the FIFO
Table 17 – Description of Command
Symbols
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POWER MANAGEMENT
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119
Note 5 under table
Fan Tachometer Inputs, second paragraph
under fan count equation
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Table 58 – Runtime Register Block
Summary
Table 59 – PME, SMI, GPIO, FAN Register
Description
Table 62 – Chip Level Registers
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168
Table 72 – KYBD, Logical Device 7 [Logical
Device Number = 0x07]
DC Electrical Characteristics
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PACKAGE OUTLINE
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