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參數(shù)資料
| 型號： | LPC47M14N-NC |
| 廠商： | SMSC Corporation |
| 英文描述： | MULTI DVI TRANSMITTER -FIBER |
| 中文描述： | 128引腳ENGANCED超級I / O與LPC接口和USB集線器控制器 |
| 文件頁數(shù)： | 94/205頁 |
| 文件大?。?/td> | 1219K |
| 代理商： | LPC47M14N-NC |
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SMSC DS – LPC47M14X
Page 94
Rev. 03/19/2001
the FIFO. If at this time the FIFO is full, it can be completely emptied in a single burst, otherwise a minimum of (16-
<threshold>) bytes may be read from the FIFO in a single burst.
Programmed I/O - Transfers from the Host to the FIFO
In the forward direction an interrupt occurs when serviceIntr is 0 and there are writeIntrThreshold or more bytes free in
the FIFO. At this time if the FIFO is empty it can be filled with a single burst before the empty bit needs to be re-read.
Otherwise it may be filled with writeIntrThreshold bytes.
writeIntrThreshold = (16-<threshold>) free bytes in FIFO
An interrupt is generated when serviceIntr is 0 and the number of bytes in the FIFO is less than or equal to <threshold>.
(If the threshold = 12, then the interrupt is set whenever there are 12 or less bytes of data in the FIFO.) The host must
respond to the request by writing data to the FIFO. If at this time the FIFO is empty, it can be completely filled in a single
burst, otherwise a minimum of (16-<threshold>) bytes may be written to the FIFO in a single burst. This process is
repeated until the last byte is transferred into the FIFO.
6.10 POWER MANAGEMENT
Power management capabilities are provided for the following logical devices: floppy disk, UART 1, UART 2 and the
parallel port. For each logical device, two types of power management are provided: direct powerdown and auto
powerdown.
FDC Power Management
Direct power management is controlled by CR22. Refer to CR22 for more information.
Auto Power Management is enabled by CR23-B0. When set, this bit allows FDC to enter powerdown when all of the
following conditions have been met:
1) The motor enable pins of register 3F2H are inactive (zero).
2) The part must be idle; MSR=80H and INT = 0 (INT may be high even if MSR = 80H due to polling interrupts).
3) The head unload timer must have expired.
4) The Auto powerdown timer (10msec) must have timed out.
An internal timer is initiated as soon as the auto powerdown command is enabled. The part is then powered down when
all the conditions are met.
Disabling the auto powerdown mode cancels the timer and holds the FDC block out of auto powerdown.
Note:
At least 8us delay should be added when exiting FDC Auto Powerdown mode. If the operating environment is
such that this delay cannot be guaranteed, the auto powerdown mode should not be used and Direct powerdown
mode should be used instead. The Direct powerdown mode requires at least 8us delay at 250K bits/sec
configuration and 4us delay at 500K bits/sec. The delay should be added so that the internal microcontroller can
prepare itself to accept commands.
DSR From Powerdown
If DSR powerdown is used when the part is in auto powerdown, the DSR powerdown will override the auto powerdown.
However, when the part is awakened from DSR powerdown, the auto powerdown will once again become effective.
Wake Up From Auto Powerdown
If the part enters the powerdown state through the auto powerdown mode, then the part can be awakened by reset or by
appropriate access to certain registers.
If a hardware or software reset is used then the part will go through the normal reset sequence. If the access is through
the selected registers, then the FDC resumes operation as though it was never in powerdown. Besides activating the
PCI_RESET# pin or one of the software reset bits in the DOR or DSR, the following register accesses will wake up the
part:
1) Enabling any one of the motor enable bits in the DOR register (reading the DOR does not awaken the part).
2) A read from the MSR register.
3) A read or write to the Data register.
Once awake, the FDC will reinitiate the auto powerdown timer for 10 ms. The part will powerdown again when all
the powerdown conditions are satisfied.
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