- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄358934 > LPC47M14D-NC (SMSC Corporation) POS LASER SCANNER CABLE B PDF資料下載
參數(shù)資料
| 型號： | LPC47M14D-NC |
| 廠商： | SMSC Corporation |
| 英文描述： | POS LASER SCANNER CABLE B |
| 中文描述： | 128引腳ENGANCED超級I / O與LPC接口和USB集線器控制器 |
| 文件頁數(shù)： | 22/205頁 |
| 文件大?。?/td> | 1219K |
| 代理商： | LPC47M14D-NC |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁當(dāng)前第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁
SMSC DS – LPC47M14X
Page 22
Rev. 03/19/2001
6.3.5
The LPC47M14x is the target for I/O cycles. I/O cycles are initiated by the host for register or FIFO accesses, and
will generally have minimal Sync times. The minimum number of wait-states between bytes is 1. EPP cycles will
depend on the speed of the external device, and may have much longer Sync times.
Data transfers are assumed to be exactly 1-byte. If the CPU requested a 16 or 32-bit transfer, the host will break it
up into 8-bit transfers.
See the “Low Pin Count (LPC) Interface Specification”
Revision 1.0
, Section 5.2, for the sequence of cycles for the
I/O Read and Write cycles.
6.3.6
DMA Read and Write Cycles
DMA read cycles involve the transfer of data from the host (main memory) to the LPC47M14x. DMA write cycles
involve the transfer of data from the LPC47M14x to the host (main memory). Data will be coming from or going to a
FIFO and will have minimal Sync times. Data transfers to/from the LPC47B10x are 1, 2 or 4 bytes.
See the “Low Pin Count (LPC) Interface Specification”
Revision 1.0
, Section 6.4, for the field definitions and the
sequence of the DMA Read and Write cycles.
6.3.7
DMA Protocol
DMA on the LPC bus is handled through the use of the LDRQ# lines from the LPC47M14x and special encodings on
LAD[3:0] from the host.
The DMA mechanism for the LPC bus is described in the “Low Pin Count (LPC) Interface Specification,” Revision
1.0.
6.3.8
Power Management
CLOCKRUN Protocol
The CLKRUN# pin is not implemented in the LPC47M14x.
See the “Low Pin Count (LPC) Interface Specification”
Revision 1.0
, Section 8.1.
LPCPD Protocol
See the “Low Pin Count (LPC) Interface Specification”
Revision 1.0
, Section 8.2.
6.3.9
SYNC Protocol
See the “Low Pin Count (LPC) Interface Specification”
Revision 1.0
, Section 4.2.1.8 for a table of valid SYNC values.
Typical Usage
The SYNC pattern is used to add wait states. For read cycles, the LPC47M14x immediately drives the SYNC pattern
upon recognizing the cycle. The host immediately drives the sync pattern for write cycles. If the LPC47M14x needs
to assert wait states, it does so by driving 0101 or 0110 on LAD[3:0] until it is ready, at which point it will drive 0000 or
1001. The LPC47M14x will choose to assert 0101 or 0110, but not switch between the two patterns.
The data (or wait state SYNC) will immediately follow the 0000 or 1001 value. The SYNC value of 0101 is intended
to be used for normal wait states, wherein the cycle will complete within a few clocks. The LPC47M14x uses a SYNC
of 0101 for all wait states in a DMA transfer.
The SYNC value of 0110 is intended to be used where the number of wait states is large. This is provided for EPP
cycles, where the number of wait states could be quite large (>1 microsecond). However, the LPC47M14x uses a
SYNC of 0110 for all wait states in an I/O transfer.
The SYNC value is driven within 3 clocks.
SYNC Timeout
The SYNC value is driven within 3 clocks. If the host observes 3 consecutive clocks without a valid SYNC pattern, it
will abort the cycle.
The LPC47M14x does not assume any particular timeout. When the host is driving SYNC, it may have to insert a
very large number of wait states, depending on PCI latencies and retries.
I/O Read and Write Cycles
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LPC47M14F-NC | DEVICE BOX 1 3/8"DX3/4"LX SCA- |
| LPC47M14G-NC | Electrical Duct/Raceway Fitting; |
| LPC47M14J-NC | 4 PR 568B RJ45 STR UTP CASHD-ST54PVU-568B-BG-015 |
| LPC47M14N-NC | MULTI DVI TRANSMITTER -FIBER |
| LPC47M14O-NC | CAT5 AUDIO/VIDEO SPLITTER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LPC47M14E-NC | 制造商:SMSC 制造商全稱:SMSC 功能描述:128 PIN ENGANCED SUPER I/O CONTROLLER WITH AN LPC INTERFACE AND USB HUB |
| LPC47M14F-NC | 制造商:SMSC 制造商全稱:SMSC 功能描述:128 PIN ENGANCED SUPER I/O CONTROLLER WITH AN LPC INTERFACE AND USB HUB |
| LPC47M14G-NC | 制造商:SMSC 制造商全稱:SMSC 功能描述:128 PIN ENGANCED SUPER I/O CONTROLLER WITH AN LPC INTERFACE AND USB HUB |
| LPC47M14H-NC | 制造商:SMSC 制造商全稱:SMSC 功能描述:128 PIN ENGANCED SUPER I/O CONTROLLER WITH AN LPC INTERFACE AND USB HUB |
| LPC47M14I-NC | 制造商:SMSC 制造商全稱:SMSC 功能描述:128 PIN ENGANCED SUPER I/O CONTROLLER WITH AN LPC INTERFACE AND USB HUB |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。