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參數(shù)資料
| 型號(hào)： | LPC47M14A-NC |
| 廠商： | SMSC Corporation |
| 英文描述： | 128 PIN ENGANCED SUPER I/O CONTROLLER WITH AN LPC INTERFACE AND USB HUB |
| 中文描述： | 128引腳ENGANCED超級(jí)I / O與LPC接口和USB集線器控制器 |
| 文件頁(yè)數(shù)： | 179/205頁(yè) |
| 文件大?。?/td> | 1219K |
| 代理商： | LPC47M14A-NC |
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SMSC DS – LPC47M14X
Page 179
Rev. 03/19/2001
PARAMETER
Differential Rise/Fall Time
Matching
SYM
TRFM
CONDITIONS
(NOTES 1, 2, 3)
(TR/TF)
Note 9
Steady State Drive
MIN
90
MAX
111.11
UNIT
%
Drive Output Impedance
DRIVER CHARACTERISTICS (Low-Speed)
Transition Time:
Rise Time
Fall Time
Differential Rise/Fall Time
Matching
ZDRV
28
44
TR
TF
TRFM
Note 4,5 and FIGURE 10
FIGURE 12
FIGURE 12
(TR/TF)
Note 9
75
75
80
300
300
125
ns
ns
%
DATA TRANSFER TIMINGS
Full Speed Data Rate
Frame Interval
Clock Period
Source
Jitter
(including
tolerance):
To next Transition
For Paired Transitions
TDRATE
TFRAME
TPERIOD
TDJ1
TDJ2
TDEOP
Notes 8, 10, & 12
Note 8
Note 10
Note 6, 7, & 9
11.9700
0.9995
80
-3.5
-4.0
-2
12.0300
1.0005
86
3.5
4.0
5
Mbs
ms
ns
ns
ns
ns
Total
frequency
FIGURE 14
Source
Differential Transition to
SEO Transition
Receiver Jitter:
To next Transition
For Paired Transitions
Source SEO interval of
EOP
Receiver SEO interval of
EOP
Width of SEO interval
during
transition
Jitter
for
Note 7 and FIGURE 15
TJR1
TJR2
TEOPT
Note 7 and FIGURE 16
-18.5
-9
160
18.5
9.0
175
ns
ns
ns
Note 7 and FIGURE 15
TEOPR
Note 7 and FIGURE 15
82
ns
differential
TFST
Note 11
14
ns
Note 1:
All voltages are measured from the local ground potential, unless otherwise specified.
Note 2:
All timing use a capacitive load (CL) to ground of 50pF, unless otherwise specified.
Note 3:
Full speed timings have a 1.5K
pull-up to a voltage of 3.0V - 3.6V on the D+ data line.
Note 4:
Measured from 10% to 90% of the data signals.
Note 5:
The rising and falling edges should be smoothly transitioning (monotonic).
Note 6:
Timing differences between the differential data signals.
Note 7:
Measured at crossover point of differential data signals.
Note 8:
For a more detailed description of the Data Signaling Rate and the Frame Interval see sections 7.1.11 and
7.1.12 in the USB Spec 1.1.
Note 9:
Excluding the first transition from the idle state.
Note 10:
The accuracy of the host controller’s data rate must be known and controlled to better than
±
0.05%
Note 11:
During differential signal transitions both PD+ and PD- may temporarily be less that
VIH(min). This period can be up to 14ns.
Note 12:
The data-rate tolerance for host, hub, and full-speed functions is
±
0.25%
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