參數(shù)資料
型號(hào): LPC2927FBD144
廠(chǎng)商: NXP SEMICONDUCTORS
元件分類(lèi): 微控制器/微處理器
英文描述: ARM9 microcontroller with CAN, LIN, and USB
中文描述: 32-BIT, FLASH, 125 MHz, RISC MICROCONTROLLER, PQFP144
封裝: 20 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT486-1, LQFP-144
文件頁(yè)數(shù): 38/95頁(yè)
文件大?。?/td> 1855K
代理商: LPC2927FBD144
LPC2926_27_29
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 5 — 28 September 2010
38 of 95
NXP Semiconductors
LPC2926/2927/2929
ARM9 microcontroller with CAN, LIN, and USB
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I
2
C is a multi-master bus, and it can be
controlled by more than one bus master connected to it.
The main features if the I
2
C-bus interfaces are:
I
2
C0/1 use standard I/O pins with bit rates of up to 400 kbit/s (Fast I
2
C-bus) and do
not support powering off of individual devices connected to the same bus lines.
Easy to configure as master, slave, or master/slave.
Programmable clocks allow versatile rate control.
Bidirectional data transfer between masters and slaves.
Multi-master bus (no central master).
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
The I
2
C-bus can be used for test and diagnostic purposes.
All I
2
C-bus controllers support multiple address recognition and a bus monitor mode.
6.14.3.1
Pin description
Table 22.
Symbol
I2C SCL0/1
I2C SDA0/1
[1]
Note that the pins are not I
2
C-bus compliant open-drain pins.
6.15 Modulation and sampling control subsystem
The Modulation and Sampling Control Subsystem (MSCSS) in the LPC2926/2927/2929
includes four Pulse Width Modulators (PWMs), three 10-bit successive approximation
Analog-to-Digital Converters (ADCs) and two timers.
The key features of the MSCSS are:
Two 10-bit, 400 ksample/s, 8-channel ADCs with 3.3 V inputs and various trigger-
start options
One 10-bit, 400 ksample/s, 8-channel ADC with 5 V inputs (5 V measurement range)
and various trigger-start options
Four 6-channel PWMs (Pulse Width Modulators) with capture and trap functionality
Two dedicated timers to schedule and synchronize the PWMs and ADCs
Quadrature encoder interface
6.15.1
Functional description
The MSCSS contains Pulse Width Modulators (PWMs), Analog-to-Digital Converters
(ADCs) and timers.
I
2
C-bus pins
[1]
Pin name
SCL0/1
SDA0/1
Direction
I/O
I/O
Description
I2C clock input/output
I2C data input/output
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