參數(shù)資料
型號(hào)： LPC2460FBD208
廠商： NXP Semiconductors N.V.
元件分類： 數(shù)學(xué)處理器
英文描述： Flashless 16-bit-32-bit microcontroller; Ethernet, CAN, ISP-IAP, USB 2.0 device-host-OTG, external memory interface
封裝： LPC2420FBD208<SOT459-1 (LQFP208)|<<http://www.nxp.com/packages/SOT459-1.html<1<Always Pb-free,;LPC2420FET208<SOT950-1 (TFBGA208)|<<http://www.nxp.com/packages/SOT950-1.ht
文件頁數(shù)： 33/86頁
文件大小： 496K
代理商： LPC2460FBD208
LPC2420_60
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 6.1 — 22 September 2011
33 of 86
NXP Semiconductors
LPC2420/2460
Flashless 16-bit/32-bit microcontroller
–
Wake-on-LAN power management support allows system wake-up: using the
receive filters or a magic frame detection filter.
Physical interface:
–
Attachment of external PHY chip through standard MII or RMII interface.
–
PHY register access is available via the MIIM interface.
7.10 USB interface
The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a
host and one or more (up to 127) peripherals. The host controller allocates the USB
bandwidth to attached devices through a token-based protocol. The bus supports hot
plugging and dynamic configuration of the devices. All transactions are initiated by the
host controller.
The LPC2420/2460 USB interface includes a device, host, and OTG controller. Details on
typical USB interfacing solutions can be found in
Section 14.2 “Suggested USB interface
solutions” on page 69
7.10.1
USB device controller
The device controller enables 12 Mbit/s data exchange with a USB host controller. It
consists of a register interface, serial interface engine, endpoint buffer memory, and a
DMA controller. The serial interface engine decodes the USB data stream and writes data
to the appropriate endpoint buffer. The status of a completed USB transfer or error
condition is indicated via status registers. An interrupt is also generated if enabled. When
enabled, the DMA controller transfers data between the endpoint buffer and the USB
RAM.
7.10.1.1
Features
Fully compliant with
USB 2.0 specification
(full speed).
Supports 32 physical (16 logical) endpoints with a 4 kB endpoint buffer RAM.
Supports Control, Bulk, Interrupt and Isochronous endpoints.
Scalable realization of endpoints at run time.
Endpoint Maximum packet size selection (up to USB maximum specification) by
software at run time.
Supports SoftConnect and GoodLink features.
While USB is in the Suspend mode, LPC2420/2460 can enter one of the reduced
power modes and wake up on USB activity.
Supports DMA transfers with the DMA RAM of 16 kB on all non-control endpoints.
Allows dynamic switching between CPU-controlled and DMA modes.
Double buffer implementation for Bulk and Isochronous endpoints.
7.10.2
USB host controller
The host controller enables full- and low-speed data exchange with USB devices attached
to the bus. It consists of register interface, serial interface engine and DMA controller. The
register interface complies with the OHCI specification.
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