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參數(shù)資料
| 型號(hào)： | LPC2292FET144 |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 數(shù)學(xué)處理器 |
| 英文描述： | 16-32-bit ARM microcontrollers; 256 kB ISP-IAP flash with CAN, 10-bit ADC and external memory interface |
| 封裝： | LPC2292FBD144/01<SOT486-1 (LQFP144)|<<http://www.nxp.com/packages/SOT486-1.html<1<Always Pb-free,;LPC2292FET144/01<SOT569-1 (TFBGA144)|<<http://www.nxp.com/packages/SOT56 |
| 文件頁數(shù)： | 26/54頁 |
| 文件大?。?/td> | 428K |
| 代理商： | LPC2292FET144 |
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LPC2292_2294
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 8 — 8 June 2011
26 of 54
NXP Semiconductors
LPC2292/2294
16/32-bit ARM microcontrollers with external memory interface
The Wake-up Timer monitors the crystal oscillator as the means of checking whether it is
safe to begin code execution. When power is applied to the chip, or some event caused
the chip to exit Power-down mode, some time is required for the oscillator to produce a
signal of sufficient amplitude to drive the clock logic. The amount of time depends on
many factors, including the rate of V
DD
ramp (in the case of power-on), the type of crystal
and its electrical characteristics (if a quartz crystal is used), as well as any other external
circuitry (e.g. capacitors), and the characteristics of the oscillator itself under the existing
ambient conditions.
6.19.4
Code security (Code Read Protection - CRP)
This feature of the LPC2292/2294/01 allows the user to enable different levels of security
in the system so that access to the on-chip flash and use of the JTAG and ISP can be
restricted. When needed, CRP is invoked by programming a specific pattern into a
dedicated flash location. IAP commands are not affected by the CRP.
There are three levels of the Code Read Protection.
CRP1 disables access to chip via the JTAG and allows partial flash update (excluding
flash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is
required and flash field updates are needed but all sectors can not be erased.
CRP2 disables access to chip via the JTAG and only allows full flash erase and update
using a reduced set of the ISP commands.
Running an application with level CRP3 selected fully disables any access to chip via the
JTAG pins and the ISP. This mode effectively disables ISP override using P0[14] pin, too.
It is up to the user’s application to provide (if needed) flash update mechanism using IAP
calls or call reinvoke ISP command to enable flash update via UART0.
Remark:
Devices without a /00 or /01 in the name have only a security level equivalent to
CRP2 available.
6.19.5
External interrupt inputs
The LPC2292/2294 include up to nine edge or level sensitive External Interrupt Inputs as
selectable pin functions. When the pins are combined, external events can be processed
as four independent interrupt signals. The External Interrupt Inputs can optionally be used
to wake up the processor from Power-down mode.
6.19.6
Memory mapping control
The Memory Mapping Control alters the mapping of the interrupt vectors that appear
beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the on-chip
flash memory, or to the on-chip static RAM. This allows code running in different memory
spaces to have control of the interrupts.
CAUTION
If level three Code Read Protection (CRP3) is selected, no future factory testing can be
performed on the device.
相關(guān)PDF資料 |
PDF描述 |
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| LPC2294HBD144 | 16-32-bit ARM microcontrollers; 256 kB ISP-IAP flash with CAN, 10-bit ADC and external memory interface |
| LPC2361FBD100 | Single-chip 16-bit-32-bit MCU; up to 128 kB flash with ISP-IAP, Ethernet, USB 2.0 device-host-OTG, CAN, and 10-bit ADC-DAC |
| LPC2362FBD100 | Single-chip 16-bit-32-bit MCU; up to 128 kB flash with ISP-IAP, Ethernet, USB 2.0 device-host-OTG, CAN, and 10-bit ADC-DAC |
| LPC2364FBD100 | ARM7 with 128 kB flash, 34 kB SRAM, Ethernet, USB 2.0 Device, CAN, and 10-bit ADC |
| LPC2365FBD100 | ARM7 with 256 kB flash, 58 kB SRAM, Ethernet and 10-bit ADC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LPC2292FET144,551 | 功能描述:ARM微控制器 - MCU 256K FL/16K RM/2 CAN/ADC/EXT B RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:72 MHz 程序存儲(chǔ)器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風(fēng)格:SMD/SMT |
| LPC2292FET144/00 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:16/32-bit ARM microcontrollers; 256 kB ISP/IAP flash with CAN, 10-bit ADC and external memory interface |
| LPC2292FET144/01 | 制造商:NXP Semiconductors 功能描述:MCU, 16BIT/32BIT, 60MHZ, TFBGA-144 制造商:NXP Semiconductors 功能描述:MCU, 16BIT/32BIT, 60MHZ, TFBGA-144, Controller Family/Series:LPC2200, Core Size:16bit / 32bit, No. of I/O's:112, Supply Voltage Min:1.65V, Supply Voltage Max:1.95V, Digital IC Case Style:TFBGA, No. of Pins:144, Program Memory |
| LPC2292FET144/01,5 | 功能描述:ARM微控制器 - MCU ARM7 256KF/16KR/2CAN RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:72 MHz 程序存儲(chǔ)器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風(fēng)格:SMD/SMT |
| LPC2292FET144/015 | 制造商:NXP Semiconductors 功能描述:LPC2292FET144/TFBGA144/TRAYBDP |
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