參數(shù)資料
型號(hào): LPC2292FBD144,551
廠商: NXP Semiconductors
文件頁數(shù): 26/54頁
文件大?。?/td> 0K
描述: IC ARM7 MCU FLASH 256K 144-LQFP
標(biāo)準(zhǔn)包裝: 60
系列: LPC2200
核心處理器: ARM7
芯體尺寸: 16/32-位
速度: 60MHz
連通性: CAN,EBI/EMI,I²C,Microwire,SPI,SSI,SSP,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 112
程序存儲(chǔ)器容量: 256KB(256K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 16K x 8
電壓 - 電源 (Vcc/Vdd): 1.65 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 144-LQFP
包裝: 托盤
配用: OM10091-ND - KIT DEV PHYCORE-ARM7/LPC2220
568-1757-ND - BOARD EVAL FOR LPC220X ARM MCU
其它名稱: 568-1230
935275656551
LPC2292FBD144-S
LPC2292_2294
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 8 — 8 June 2011
32 of 54
NXP Semiconductors
LPC2292/2294
16/32-bit ARM microcontrollers with external memory interface
[1]
Typical ratings are not guaranteed. The values listed are at room temperature (+25
C), nominal supply voltages.
[2]
Internal rail.
[3]
External rail.
[4]
Including voltage on outputs in 3-state mode.
[5]
VDD(3V3) supply voltages must be present.
[6]
3-state outputs go into 3-state mode when VDD(3V3) is grounded.
[7]
Accounts for 100 mV voltage drop in all supply lines.
[8]
Allowed as long as the current limit does not exceed the maximum current allowed by the device.
[9]
Minimum condition for VI = 4.5 V, maximum condition for VI =5.5 V.
[10] Applies to P1[25:16].
[11] See the LPC2119/2129/2194/2292/2294 User Manual.
[12] To VSS.
[1]
Conditions: VSSA =0V, VDDA =3.3 V.
[2]
The ADC is monotonic, there are no missing codes.
[3]
The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 5.
[4]
The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after
appropriate adjustment of gain and offset errors. See Figure 5.
[5]
The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the
ideal curve. See Figure 5.
[6]
The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset
error, and the straight line which fits the ideal transfer curve. See Figure 5.
[7]
The absolute voltage error (ET) is the maximum difference between the center of the steps of the actual transfer curve of the
non-calibrated ADC and the ideal transfer curve. See Figure 5.
Oscillator pins
Vi(XTAL1)
input voltage on pin XTAL1
0
-
1.8
V
Vo(XTAL2)
output voltage on pin
XTAL2
0-
1.8
V
Table 7.
Static characteristics …continued
Tamb = 40 C to +125 C, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ[1]
Max
Unit
Table 8.
ADC static characteristics
VDDA = 2.5 V to 3.6 V; Tamb = 40 C to +125 C unless otherwise specified. ADC frequency 4.5 MHz.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIA
analog input voltage
0
-
VDDA
V
Cia
analog input
capacitance
--
1
pF
ED
differential linearity
error
--
1LSB
EL(adj)
integral non-linearity
2LSB
EO
offset error
3LSB
EG
gain error
0.5
%
ET
absolute error
4LSB
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