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參數(shù)資料
| 型號(hào)： | LPC2220 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 16/32-bit ARM microcontrollers; flashless with 64 kB, with 10-bit ADC and external memory interface |
| 中文描述： | 16/32位 ARM微控制器；64KB的閃存；10位模數(shù)轉(zhuǎn)換和外部存儲(chǔ)器接口 |
| 文件頁數(shù)： | 23/49頁 |
| 文件大?。?/td> | 255K |
| 代理商： | LPC2220 |
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9397 750 14061
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02— 30 May 2005
23 of 49
Philips Semiconductors
LPC2210/2220
16/32-bit ARM microcontrollers with external memory interface
6.12 UARTs
The LPC2210/2220 contains two UARTs. One UART provides a full modem control
handshake interface, the other provides only transmit and receive data lines.
6.12.1
Features
16 byte Receive and Transmit FIFOs.
Register locations conform to ‘550’ industry standard.
Receiver FIFO trigger points at 1, 4, 8, and 14 bytes
Built-in baud rate generator.
Standard modem interface signals included on UART1.
LPC2220 provides enhanced UARTs with fractional baud-rate generators,
mechanism for software flow control, and hardware (CTS/RTS) flow control on UART1
only.
6.13 I
2
C-bus serial I/O controller
The I
2
C-bus is a bidirectional bus for inter-IC control using only two wires: a serial clock
line (SCL), and a serial data line (SDA). Each device is recognized by a unique address
and can operate as either a receiver-only device (e.g., an LCD driver or a transmitter with
the capability to both receive and send information (such as memory)). Transmitters
and/or receivers can operate in either master or slave mode, depending on whether the
chip has to initiate a data transfer or is only addressed. The I
2
C-bus is a multi-master bus,
it can be controlled by more than one bus master connected to it.
The I
2
C-bus implemented in LPC2210/2220 supports a bit rate up to 400 kbit/s (Fast
I
2
C-bus).
6.13.1
Features
Compliant with standard I
2
C-bus interface.
Easy to configure as Master, Slave, or Master/Slave.
Programmable clocks allow versatile rate control.
Bidirectional data transfer between masters and slaves.
Multi-master bus (no central master).
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
The I
2
C-bus may be used for test and diagnostic purposes.
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| LPC2220FBD144,551-CUT TAPE | 制造商:NXP 功能描述:LPC2220 Series 16 kB 60 MHz 16/32-Bit Flashless ARM Microcontroller - LQFP-144 |
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