參數(shù)資料
型號: LPC2214FBD144
廠商: NXP Semiconductors N.V.
元件分類: 數(shù)學處理器
英文描述: Single-chip 16-32-bit ARM microcontrollers; 128-256 kB ISP-IAP flash with 10-bit ADC and external memory interface
封裝: LPC2212FBD144/01<SOT486-1 (LQFP144)|<<http://www.nxp.com/packages/SOT486-1.html<1<Always Pb-free,;LPC2214FBD144/01<SOT486-1 (LQFP144)|<<http://www.nxp.com/packages/SOT486
文件頁數(shù): 39/47頁
文件大?。?/td> 337K
代理商: LPC2214FBD144
LPC2212_2214
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 14 June 2011
39 of 47
NXP Semiconductors
LPC2212/2214
Single-chip 16/32-bit ARM microcontrollers
[1]
Except on initial access, in which case the address is set up T
cy(CCLK)
earlier.
T
cy(CCLK)
=
1
CCLK.
Latest of address valid, CS LOW, OE LOW to data valid.
[2]
[3]
[4]
Address valid to data valid.
[5]
Earliest of CS HIGH, OE HIGH, address change to data invalid.
[1]
See the
LPC2114/2124/2212/2214 User Manual
for a description of the WSTn bits.
t
BLSHDNV
BLS HIGH to data invalid
time
XCLK HIGH to data valid
time
XCLK HIGH to WE LOW
time
XCLK HIGH to BLS LOW
time
XCLK HIGH to WE HIGH
time
XCLK HIGH to BLS HIGH
time
XCLK HIGH to data invalid
time
[2]
(2
T
cy(CCLK)
)
5
-
(2
T
cy(CCLK)
) + 5
ns
t
CHDV
-
-
10
ns
t
CHWEL
-
-
10
ns
t
CHBLSL
-
-
10
ns
t
CHWEH
-
-
10
ns
t
CHBLSH
-
-
10
ns
t
CHDNV
-
-
10
ns
Table 10.
C
L
= 25 pF; T
amb
= 40
C.
Symbol
Parameter
External memory interface dynamic characteristics
…continued
Conditions
Min
Typ Max
Unit
Table 11.
Access cycle
Standard read access specifications
Max frequency
WST
[1]
setting
WST
0; round up to
integer
Memory access time requirement
standard read
standard write
burst read - initial
burst read - subsequent 3
N/A
f
MAX
20
ns
+
t
RAM
-------------------------------
WST1
t
t
cy CCLK
-------------------------------
2
t
RAM
t
cy CCLK
2
WST1
+
20
ns
f
MAX
+
t
WRITE
5
ns
---------------------------------
WST2
t
-------------------------------------------
t
5
+
t
cy CCLK
t
WRITE
t
cy CCLK
1
WST2
+
5
ns
f
MAX
20
ns
+
t
INIT
-------------------------------
WST1
t
t
cy CCLK
-------------------------------
2
t
INIT
t
cy CCLK
2
WST1
+
20
ns
f
MAX
+
t
ROM
20
ns
--------------------------------
t
ROM
t
cy CCLK
20
ns
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