參數(shù)資料
型號(hào)： LPC214x
廠商： NXP Semiconductors N.V.
英文描述： Single-chip 16-bit/32-bit microcontrollers; up to 512 kB flash with ISP/IAP, USB 2.0 full-speed device, 10-bit ADC and DAC
中文描述： 單芯片16-bit/32-bit微控制器，高達(dá)512的ISP /國(guó)際檢察官聯(lián)合會(huì)的USB 2.0全速設(shè)備，10位ADC和DAC kB閃存
文件頁(yè)數(shù)： 17/38頁(yè)
文件大?。?/td> 193K
代理商： LPC214X
9397 750 14985
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Preliminary data sheet
Rev. 01 — 3 October 2005
17 of 38
Philips Semiconductors
LPC2141/42/44/46/48
Single-chip 16-bit/32-bit microcontrollers
6.11.1
Features
16 byte Receive and Transmit FIFOs.
Register locations conform to ‘550 industry standard.
Receiver FIFO trigger points at 1, 4, 8, and 14 bytes
Built-in fractional baud rate generator covering wide range of baud rates without a
need for external crystals of particular values.
Transmission FIFO control enables implementation of software (XON/XOFF) flow
control on both UARTs.
LPC2144/46/48 UART1 equipped with standard modem interface signals. This
module also provides full support for hardware flow control (auto-CTS/RTS).
6.12 I
2
C-bus serial I/O controller
The LPC2141/42/44/46/48 each contain two I
2
C-bus controllers.
The I
2
C-bus is bidirectional, for inter-IC control using only two wires: a serial clock line
(SCL), and a serial data line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (e.g., an LCD driver or a transmitter with the
capability to both receive and send information (such as memory)). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I
2
C-bus is a multi-master bus, it can be
controlled by more than one bus master connected to it.
The I
2
C-bus implemented in LPC2141/42/44/46/48 supports bit rates up to 400 kbit/s
(Fast I
2
C-bus).
6.12.1
Features
Compliant with standard I
2
C-bus interface.
Easy to configure as master, slave, or master/slave.
Programmable clocks allow versatile rate control.
Bidirectional data transfer between masters and slaves.
Multi-master bus (no central master).
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
The I
2
C-bus can be used for test and diagnostic purposes.
6.13 SPI serial I/O controller
The LPC2141/42/44/46/48 each contain one SPI controller. The SPI is a full duplex serial
interface, designed to handle multiple masters and slaves connected to a given bus. Only
a single master and a single slave can communicate on the interface during a given data
transfer. During a data transfer the master always sends a byte of data to the slave, and
the slave always sends a byte of data to the master.
相關(guān)PDF資料
PDF描述
LPC2212 16/32-bit ARM microcontrollers; 128/256 kB ISP/IAP Flash with 10-bit ADC and external memory interface
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LPC2220 16/32-bit ARM microcontrollers; flashless with 64 kB, with 10-bit ADC and external memory interface
LPC2364FB100 Single-chip 16-bit/32-bit microcontrollers; up to 512 kB flash with ISP/IAP, Ethernet, USB 2.0, CAN, and 10-bit ADC/DAC
LPC2364 Single-chip 16-bit/32-bit microcontrollers; up to 512 kB flash with ISP/IAP, Ethernet, USB 2.0, CAN, and 10-bit ADC/DAC
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參數(shù)描述
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