參數(shù)資料
型號： LPC2142FBD64
廠商： NXP Semiconductors N.V.
元件分類： 數(shù)學處理器
英文描述： Single-chip 16-bit-32-bit microcontrollers; up to 512 kB flash with ISP-IAP, USB 2.0 full-speed device, 10-bit ADC and DAC
封裝： LPC2141FBD64<SOT314-2 (LQFP64)|<<http://www.nxp.com/packages/SOT314-2.html<1<Always Pb-free,;LPC2142FBD64<SOT314-2 (LQFP64)|<<http://www.nxp.com/packages/SOT314-2.html<
文件頁數(shù)： 30/45頁
文件大?。?/td> 391K
代理商： LPC2142FBD64
LPC2141_42_44_46_48
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 12 August 2011
30 of 45
NXP Semiconductors
LPC2141/42/44/46/48
Single-chip 16-bit/32-bit microcontrollers
9. Dynamic characteristics
[1]
Characterized but not implemented as production test. Guaranteed by design.
[1]
Parameters are valid over operating temperature range unless otherwise specified.
[2]
Typical ratings are not guaranteed. The values listed are at room temperature (25
C), nominal supply voltages.
[3]
Bus capacitance C
b
in pF, from 10 pF to 400 pF.
Table 6.
C
L
= 50 pF; R
pu
= 1.5 k
on D+ to V
DD
, unless otherwise specified.
Symbol
Parameter
t
r
rise time
t
f
fall time
t
FRFM
differential rise and fall time
matching
V
CRS
output signal crossover voltage
t
FEOPT
source SE0 interval of EOP
t
FDEOP
source jitter for differential transition
to SE0 transition
t
JR1
receiver jitter to next transition
t
JR2
receiver jitter for paired transitions
t
EOPR1
EOP width at receiver
Dynamic characteristics of USB pins (full-speed)
Conditions
10 % to 90 %
10 % to 90 %
(t
r
/t
f
)
Min
4
4
90
Typ
-
-
-
Max
20
20
110
Unit
ns
ns
%
1.3
160
2
-
-
-
2.0
175
+5
V
ns
ns
see
Figure 7
see
Figure 7
18.5
9
-
-
-
+18.5
+9
-
ns
ns
ns
10 % to 90 %
must reject as
EOP; see
Figure 7
must accept as
EOP; see
Figure 7
[1]
40
t
EOPR2
EOP width at receiver
[1]
82
-
-
ns
Table 7.
T
amb
=
40
C to +85
C for commercial applications, V
DD
over specified ranges
[1]
Symbol
Parameter
External clock
f
osc
oscillator frequency
T
cy(clk)
clock cycle time
t
CHCX
clock HIGH time
t
CLCX
clock LOW time
t
CLCH
clock rise time
t
CHCL
clock fall time
Port pins (except P0.2, P0.3, P0.11, and P0.14)
t
r(o)
output rise time
t
f(o)
output fall time
I
2
C-bus pins (P0.2, P0.3, P0.11, and P0.14)
t
f(o)
output fall time
Dynamic characteristics
Conditions
Min
Typ
[2]
Max
Unit
10
40
T
cy(clk)
0.4
T
cy(clk)
0.4
-
-
-
-
-
-
-
-
25
100
-
-
5
5
MHz
ns
ns
ns
ns
ns
-
-
10
10
-
-
ns
ns
V
IH
to V
IL
20 + 0.1
C
b
[3]
-
-
ns
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