參數(shù)資料
型號(hào)： LPC2141FBD64
廠商： NXP Semiconductors N.V.
元件分類(lèi)： 數(shù)學(xué)處理器
英文描述： Single-chip 16-bit-32-bit microcontrollers; up to 512 kB flash with ISP-IAP, USB 2.0 full-speed device, 10-bit ADC and DAC
封裝： LPC2141FBD64<SOT314-2 (LQFP64)|<<http://www.nxp.com/packages/SOT314-2.html<1<Always Pb-free,;LPC2142FBD64<SOT314-2 (LQFP64)|<<http://www.nxp.com/packages/SOT314-2.html<
文件頁(yè)數(shù)： 23/45頁(yè)
文件大小： 391K
代理商： LPC2141FBD64
LPC2141_42_44_46_48
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 12 August 2011
23 of 45
NXP Semiconductors
LPC2141/42/44/46/48
Single-chip 16-bit/32-bit microcontrollers
The Wake-up Timer monitors the crystal oscillator as the means of checking whether it is
safe to begin code execution. When power is applied to the chip, or some event caused
the chip to exit Power-down mode, some time is required for the oscillator to produce a
signal of sufficient amplitude to drive the clock logic. The amount of time depends on
many factors, including the rate of V
DD
ramp (in the case of power on), the type of crystal
and its electrical characteristics (if a quartz crystal is used), as well as any other external
circuitry (e.g. capacitors), and the characteristics of the oscillator itself under the existing
ambient conditions.
6.19.4
Brownout detector
The LPC2141/42/44/46/48 include 2-stage monitoring of the voltage on the V
DD
pins. If
this voltage falls below 2.9 V, the BOD asserts an interrupt signal to the VIC. This signal
can be enabled for interrupt; if not, software can monitor the signal by reading dedicated
register.
The second stage of low voltage detection asserts reset to inactivate the
LPC2141/42/44/46/48 when the voltage on the V
DD
pins falls below 2.6 V. This reset
prevents alteration of the flash as operation of the various elements of the chip would
otherwise become unreliable due to low voltage. The BOD circuit maintains this reset
down below 1 V, at which point the POR circuitry maintains the overall reset.
Both the 2.9 V and 2.6 V thresholds include some hysteresis. In normal operation, this
hysteresis allows the 2.9 V detection to reliably interrupt, or a regularly-executed event
loop to sense the condition.
6.19.5
Code security
This feature of the LPC2141/42/44/46/48 allow an application to control whether it can be
debugged or protected from observation.
If after reset on-chip boot loader detects a valid checksum in flash and reads 0x8765 4321
from address 0x1FC in flash, debugging will be disabled and thus the code in flash will be
protected from observation. Once debugging is disabled, it can be enabled only by
performing a full chip erase using the ISP.
6.19.6
External interrupt inputs
The LPC2141/42/44/46/48 include up to nine edge or level sensitive External Interrupt
Inputs as selectable pin functions. When the pins are combined, external events can be
processed as four independent interrupt signals. The External Interrupt Inputs can
optionally be used to wake-up the processor from Power-down mode.
Additionally capture input pins can also be used as external interrupts without the option
to wake the device up from Power-down mode.
6.19.7
Memory mapping control
The Memory Mapping Control alters the mapping of the interrupt vectors that appear
beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the on-chip
flash memory, or to the on-chip static RAM. This allows code running in different memory
spaces to have control of the interrupts.
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