參數(shù)資料
型號: LPC2131
廠商: NXP Semiconductors N.V.
英文描述: Single-chip 16/32-bit microcontrollers; 32/64/512 kB ISP/IAP Flash with 10-bit ADC and DAC
中文描述: 16/32位 單片微控制器;有10位數(shù)模/模數(shù)轉(zhuǎn)換,32/64/512kB的ISP/IAP flash閃存
文件頁數(shù): 10/41頁
文件大?。?/td> 190K
代理商: LPC2131
9397 750 14868
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Preliminary data sheet
Rev. 02 — 15 April 2005
10 of 41
Philips Semiconductors
LPC2131/2132/2134/2136/2138
Single-chip 16/32-bit microcontrollers
[1]
5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control.
[2]
5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control. If configured for an input
function, this pad utilizes built-in glitch filter that blocks pulses shorter than 3 ns.
[3]
Open drain 5 V tolerant digital I/O I
2
C-bus 400 kHz specification compatible pad. It requires external pull-up to provide an output
functionality.
[4]
5 V tolerant pad providing digital I/O (with TTL levels and hysteresis and 10 ns slew rate control) and analog input function. If configured
for an input function, this pad utilizes built-in glitch filter that blocks pulses shorter than 3 ns. When configured as an ADC input, digital
section of the pad is disabled.
[5]
5 V tolerant pad providing digital I/O (with TTL levels and hysteresis and 10 ns slew rate control) and analog output function. When
configured as the DAC output, digital section of the pad is disabled.
P1.22/
PIPESTAT1
P1.23/
PIPESTAT2
P1.24/
TRACECLK
P1.25/EXTIN0
P1.26/RTCK
40
[6]
O
PIPESTAT1 —
Pipeline Status, bit 1. Standard I/O port with internal pull-up.
36
[6]
O
PIPESTAT2 —
Pipeline Status, bit 2. Standard I/O port with internal pull-up.
32
[6]
O
TRACECLK —
Trace Clock. Standard I/O port with internal pull-up.
28
[6]
24
[6]
I
I/O
EXTIN0 —
External Trigger Input. Standard I/O with internal pull-up.
RTCK —
Returned Test Clock output. Extra signal added to the JTAG port.
Assists debugger synchronization when processor frequency varies.
Bi-directional pin with internal pull-up. LOW on RTCK while RESET is LOW
enables pins P1.31:26 to operate as Debug port after reset.
TDO —
Test Data out for JTAG interface.
TDI —
Test Data in for JTAG interface.
TCK —
Test Clock for JTAG interface.
TMS —
Test Mode Select for JTAG interface.
TRST —
Test Reset for JTAG interface.
External reset input:
A LOW on this pin resets the device, causing I/O ports
and peripherals to take on their default states, and processor execution to
begin at address 0. TTL with hysteresis, 5 V tolerant.
Input to the oscillator circuit and internal clock generator circuits.
Output from the oscillator amplifier.
Input to the RTC oscillator circuit.
Output from the RTC oscillator circuit.
Ground:
0 V reference.
P1.27/TDO
P1.28/TDI
P1.29/TCK
P1.30/TMS
P1.31/TRST
RESET
64
[6]
60
[6]
56
[6]
52
[6]
20
[6]
57
[7]
O
I
I
I
I
I
XTAL1
XTAL2
RTXC1
RTXC2
V
SS
62
[8]
61
[8]
3
[8]
5
[8]
6, 18, 25, 42,
50
59
I
O
I
O
I
V
SSA
I
Analog ground:
0 V reference. This should nominally be the same voltage
as V
SS
, but should be isolated to minimize noise and error.
3.3 V power supply:
This is the power supply voltage for the core and I/O
ports.
Analog 3.3 V power supply:
This should be nominally the same voltage as
V
DD
but should be isolated to minimize noise and error. This voltage is used
to power the on-chip PLL.
A/D converter reference:
This should be nominally the same voltage as V
DD
but should be isolated to minimize noise and error. Level on this pin is used as
a reference for A/D and D/A convertor(s).
RTC power supply:
3.3 V on this pin supplies the power to the RTC.
V
DD
23, 43, 51
I
V
DDA
7
I
V
REF
63
I
V
BAT
49
I
Table 3:
Symbol
Pin description
…continued
Pin
Type
Description
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