參數(shù)資料
型號(hào)： LPC2105FBD48
廠商： NXP Semiconductors N.V.
元件分類： 數(shù)學(xué)處理器
英文描述： Single-chip 32-bit microcontrollers; 128 kB ISP-IAP flash with 16-32-64 kB RAM
封裝： LPC2104FBD48/01<SOT313|<<<1<Always Pb-free,;LPC2105FBD48/01<SOT313|<<<1<Always Pb-free,;LPC2106FBD48/01<SOT313-2 (LQFP48)|<<http://www.nxp.com/packages/SOT313
文件頁(yè)數(shù)： 19/41頁(yè)
文件大?。?/td> 188K
代理商： LPC2105FBD48
LPC2104_2105_2106_7
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 20 June 2008
19 of 41
NXP Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
6.14.1
Features
A 32-bit Timer/Counter with a programmable 32-bit Prescaler.
Up to four (Timer 1) and three (Timer 0) 32-bit capture channels, that can take a
snapshot of the timer value when an input signal transitions. A capture event may also
optionally generate an interrupt.
Four 32-bit match registers that allow:
–
Continuous operation with optional interrupt generation on match.
–
Stop timer on match with optional interrupt generation.
–
Reset timer on match with optional interrupt generation.
Up to four (Timer 1) and three (Timer 0) external outputs corresponding to match
registers, with the following capabilities:
–
Set LOW on match.
–
Set HIGH on match.
–
Toggle on match.
–
Do nothing on match.
6.14.2
Features available in LPC2104/2105/2106/01 only
The LPC2104/2105/2106/01 can count external events on one of the capture inputs if the
external pulse lasts at least one half of the period of the PCLK. In this configuration,
unused capture lines can be selected as regular timer capture inputs or used as external
interrupts.
Timer can count cycles of either the peripheral clock (PCLK) or an externally supplied
clock.
When counting cycles of an externally supplied clock, only one of the timer’s capture
inputs can be selected as the timer’s clock. The rate of such a clock is limited to
PCLK
4
. Duration of HIGH/LOW levels on the selected CAP input cannot be shorter
than
1
(2PCLK)
.
6.15 Watchdog timer
The purpose of the Watchdog is to reset the microcontroller within a reasonable amount of
time if it enters an erroneous state. When enabled, the Watchdog will generate a system
reset if the user program fails to ‘feed’ (or reload) the Watchdog within a predetermined
amount of time.
6.15.1
Features
Internally resets chip if not periodically reloaded.
Debug mode.
Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be
disabled.
Incorrect/Incomplete feed sequence causes reset/interrupt if enabled.
Flag to indicate watchdog reset.
相關(guān)PDF資料
PDF描述
LPC2106FBD48 Single-chip 32-bit microcontrollers; 128 kB ISP-IAP flash with 16-32-64 kB RAM
LPC2106FHN48 Single-chip 32-bit microcontrollers; 128 kB ISP-IAP flash with 16-32-64 kB RAM
LPC2109FBD64 Single-chip 16-32-bit microcontrollers; 64-128-256 kB ISP-IAP flash with 10-bit ADC and CAN
LPC2119FBD64 Single-chip 16-32-bit microcontrollers; 64-128-256 kB ISP-IAP flash with 10-bit ADC and CAN
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LPC2105FBD48/00 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Single-chip 32-bit microcontrollers; 128 kB ISP/IAP flash with 16/32/64 kB RAM
LPC2105FBD48/01 制造商:NXP Semiconductors 功能描述:MCU, 16BIT/32BIT, 60MHZ, LQFP-48 制造商:NXP Semiconductors 功能描述:MCU, 16BIT/32BIT, 60MHZ, LQFP-48, Controller Family/Series:LPC2100, Core Size:16bit / 32bit, No. of I/O's:32, Supply Voltage Min:1.65V, Supply Voltage Max:1.95V, Digital IC Case Style:LQFP, No. of Pins:48, Program Memory Size:128KB,
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