- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄11967 > LPC2104FBD48/01,15 (NXP Semiconductors)IC ARM7 MCU FLASH 128K 48-LQFP PDF資料下載
參數(shù)資料
| 型號： | LPC2104FBD48/01,15 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 15/41頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ARM7 MCU FLASH 128K 48-LQFP |
| 標準包裝： | 250 |
| 系列： | LPC2100 |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 60MHz |
| 連通性： | I²C，Microwire，SPI，SSI，SSP，UART/USART |
| 外圍設備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 32 |
| 程序存儲器容量： | 128KB（128K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 16K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.65 V ~ 3.6 V |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 48-LQFP |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 704 (CN2011-ZH PDF) |
| 配用： | 568-4310-ND - EVAL BOARD LPC2158 W/LCD 568-4297-ND - BOARD EVAL LPC21XX MCB2100 622-1005-ND - USB IN-CIRCUIT PROG ARM7 LPC2K 568-1756-ND - BOARD EVAL FOR LPC210X ARM MCU |
| 其它名稱： | 568-4365 935286614151 LPC2104FBD48/01-S |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁當前第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁
LPC2104_2105_2106_7
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 20 June 2008
22 of 41
NXP Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2,
it is insured that the PLL output has a 50 % duty cycle.The PLL is turned off and bypassed
following a chip Reset and may be enabled by software. The program must congure and
activate the PLL, wait for the PLL to Lock, then connect to the PLL as a clock source. The
PLL settling time is 100
s.
6.18.3 Reset and wake-up timer
Reset has two sources on the LPC2104/2105/2106: the RESET pin and Watchdog Reset.
The RESET pin is a Schmitt trigger input pin with an additional glitch lter. Assertion of
chip Reset by any source starts the wake-up timer (see wake-up timer description below),
causing the internal chip reset to remain asserted until the external Reset is de-asserted,
the oscillator is running, a xed number of clocks have passed, and the on-chip ash
controller has completed its initialization.
When the internal Reset is removed, the processor begins executing at address 0, which
is the Reset vector. At that point, all of the processor and peripheral registers have been
initialized to predetermined values.
The wake-up timer ensures that the oscillator and other analog functions required for chip
operation are fully functional before the processor is allowed to execute instructions. This
is important at power on, all types of Reset, and whenever any of the aforementioned
functions are turned off for any reason. Since the oscillator and other functions are turned
off during Power-down mode, any wake-up of the processor from Power-down mode
makes use of the wake-up timer.
The wake-up timer monitors the crystal oscillator as the means of checking whether it is
safe to begin code execution. When power is applied to the chip, or some event caused
the chip to exit Power-down mode, some time is required for the oscillator to produce a
signal of sufcient amplitude to drive the clock logic. The amount of time depends on
many factors, including the rate of VDD ramp (in the case of power on), the type of crystal
and its electrical characteristics (if a quartz crystal is used), as well as any other external
circuitry (e.g. capacitors), and the characteristics of the oscillator itself under the existing
ambient conditions.
6.18.4 Code security (Code Read Protection - CRP)
This feature of the LPC2104/2105/2106/01 allows the user to enable different levels of
security in the system so that access to the on-chip ash and use of the JTAG and ISP
can be restricted. When needed, CRP is invoked by programming a specic pattern into a
dedicated ash location. IAP commands are not affected by the CRP.
There are three levels of the Code Read Protection:
1. CRP1 disables access to the chip via the JTAG and allows partial ash update
(excluding ash sector 0) using a limited set of the ISP commands. This mode is
useful when CRP is required and ash eld updates are needed but all sectors can
not be erased.
2. CRP2 disables access to the chip via the JTAG and only allows full ash erase and
update using a reduced set of the ISP commands.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VE-26Z-IW-F3 | CONVERTER MOD DC/DC 2V 40W |
| VE-26Z-IW-F2 | CONVERTER MOD DC/DC 2V 40W |
| VE-26Y-IY-F4 | CONVERTER MOD DC/DC 3.3V 33W |
| VE-26Y-IY-F3 | CONVERTER MOD DC/DC 3.3V 33W |
| VE-26Y-IY-F2 | CONVERTER MOD DC/DC 3.3V 33W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LPC2105 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Single-chip 32-bit microcontrollers; 128 kB ISP/IAP Flash with 64 kB/32 kB/16 kB RAM |
| LPC2105BBD48 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Single-chip 32-bit microcontrollers; 128 kB ISP/IAP flash with 16/32/64 kB RAM |
| LPC2105BBD48,151 | 功能描述:ARM微控制器 - MCU ARM7 128KF/32KR/I2C RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:72 MHz 程序存儲器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風格:SMD/SMT |
| LPC2105BBD48.151 | 制造商:NXP Semiconductors 功能描述:IC SM 32 BIT MCU WAFFLE125 制造商:NXP Semiconductors 功能描述:32BIT MCU 128K FLASH SMD LPC2105 |
| LPC2105BBD48.151 | 制造商:NXP Semiconductors 功能描述:IC 32BIT MCU 128K FLASH SMD 2105 |
發(fā)布緊急采購，3分鐘左右您將得到回復。