參數(shù)資料
型號(hào): LPC1347FHN33,551
廠商: NXP Semiconductors
文件頁(yè)數(shù): 8/77頁(yè)
文件大小: 0K
描述: IC MCU 32BIT 64KB FLASH 33HVQFN
標(biāo)準(zhǔn)包裝: 260
系列: LPC13xx
核心處理器: ARM? Cortex?-M3
芯體尺寸: 32-位
速度: 72MHz
連通性: I²C,Microwire,SPI,SSI,SSP,UART/USART,USB
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,WDT
輸入/輸出數(shù): 26
程序存儲(chǔ)器容量: 64KB(64K x 8)
程序存儲(chǔ)器類(lèi)型: 閃存
EEPROM 大?。?/td> 4K x 8
RAM 容量: 12K x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 32-VQFN 裸露焊盤(pán)
包裝: 托盤(pán)
其它名稱(chēng): 568-9600
LPC1315_16_17_45_46_47
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 3 — 20 September 2012
16 of 77
NXP Semiconductors
LPC1315/16/17/45/46/47
32-bit ARM Cortex-M3 microcontroller
PIO1_25/CT32B0_MAT1
2
1
-
I; PU
I/O
PIO1_25 — General purpose digital input/output pin.
-O
CT32B0_MAT1 — Match output 1 for 32-bit timer 0.
PIO1_26/CT32B0_MAT2/
RXD
14
11
-
I; PU
I/O
PIO1_26 — General purpose digital input/output pin.
-O
CT32B0_MAT2 — Match output 2 for 32-bit timer 0.
-I
RXD — Receiver input for USART.
PIO1_27/CT32B0_MAT3/
TXD
15
12
-
I; PU
I/O
PIO1_27 — General purpose digital input/output pin.
-O
CT32B0_MAT3 — Match output 3 for 32-bit timer 0.
-O
TXD — Transmitter output for USART.
PIO1_28/CT32B0_CAP0/
SCLK
31
24
-
I; PU
I/O
PIO1_28 — General purpose digital input/output pin.
-I
CT32B0_CAP0 — Capture input 0 for 32-bit timer 0.
-I/O
SCLK — Serial clock input/output for USART in
synchronous mode.
PIO1_29/SCK0/
CT32B0_CAP1
41
31
-
I; PU
I/O
PIO1_29 — General purpose digital input/output pin.
-I/O
SCK0 — Serial clock for SSP0.
-I
CT32B0_CAP1 — Capture input 1 for 32-bit timer 0.
PIO1_31
-
25
-
I; PU
I/O
PIO1_31 — General purpose digital input/output pin.
n.c.
25
19
-
Not connected.
n.c.
26
20
-
Not connected.
XTALIN
8
6
4
-
Input to the oscillator circuit and internal clock generator
circuits. Input voltage must not exceed 1.8 V.
XTALOUT
9
7
5
-
Output from the oscillator amplifier.
VDDA
59
-
Analog 3.3 V pad supply voltage: This should be
nominally the same voltage as VDD but should be isolated
to minimize noise and error. This voltage is used to power
the ADC. This pin should be tied to 3.3 V if the ADC is not
used.
VREFN
48
-
ADC negative reference voltage: This should be
nominally the same voltage as VSS but should be isolated
to minimize noise and error. Level on this pin is used as a
reference for ADC.
Table 3.
Pin description (LPC1315/16/17 - no USB)
Symbol
LQ
FP6
4
LQ
FP4
8
HVQFN
3
Re
set
st
ate
[1
]
Ty
p
e
Description
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