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參數(shù)資料
| 型號： | LPC1346FBD48,151 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 29/77頁 |
| 文件大?。?/td> | 0K |
| 描述： | MCU 32BIT ARM 48KB FLASH 48LQFP |
| 標準包裝： | 250 |
| 系列： | LPC13xx |
| 核心處理器： | ARM? Cortex?-M3 |
| 芯體尺寸： | 32-位 |
| 速度： | 72MHz |
| 連通性： | I²C，Microwire，SPI，SSI，SSP，UART/USART，USB |
| 外圍設(shè)備： | 欠壓檢測/復(fù)位，POR，WDT |
| 輸入/輸出數(shù)： | 40 |
| 程序存儲器容量： | 48KB（48K x 8） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大?。?/td> | 4K x 8 |
| RAM 容量： | 10K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 48-LQFP |
| 包裝： | 托盤 |
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LPC1315_16_17_45_46_47
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 3 — 20 September 2012
35 of 77
NXP Semiconductors
LPC1315/16/17/45/46/47
32-bit ARM Cortex-M3 microcontroller
7.18.5.4
Power-down mode
In Power-down mode, the LPC1315/16/17/45/46/47 is in Sleep-mode and all peripheral
clocks and all clock sources are off with the exception of watchdog oscillator if selected. In
addition all analog blocks and the flash are shut down. In Power-down mode, the user has
the option to keep the BOD circuit running for BOD protection.
The LPC1315/16/17/45/46/47 can wake up from Power-down mode via reset, selected
GPIO pins, a watchdog timer interrupt, or an interrupt generating USB port activity.
Power-down mode reduces power consumption compared to Deep-sleep mode at the
expense of longer wake-up times.
7.18.5.5
Deep power-down mode
In Deep power-down mode, power is shut off to the entire chip with the exception of the
WAKEUP pin. The LPC1315/16/17/45/46/47 can wake up from Deep power-down mode
via the WAKEUP pin.
The LPC1315/16/17/45/46/47 can be prevented from entering Deep power-down mode by
setting a lock bit in the PMU block. Locking out Deep power-down mode enables the user
to always keep the watchdog timer or the BOD running.
When entering Deep power-down mode, an external pull-up resistor is required on the
WAKEUP pin to hold it HIGH. The RESET pin must also be held HIGH to prevent it from
floating while in Deep power-down mode.
7.18.6 System control
7.18.6.1
Reset
Reset has four sources on the LPC1315/16/17/45/46/47: the RESET pin, the Watchdog
reset, power-on reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin
is a Schmitt trigger input pin. Assertion of chip reset by any source, once the operating
voltage attains a usable level, starts the IRC and initializes the flash controller.
A LOW-going pulse as short as 50 ns resets the part.
When the internal Reset is removed, the processor begins executing at address 0, which
is initially the Reset vector mapped from the boot block. At that point, all of the processor
and peripheral registers have been initialized to predetermined values.
An external pull-up resistor is required on the RESET pin if Deep power-down mode is
used.
7.18.6.2
Brownout detection
The LPC1315/16/17/45/46/47 includes up to four levels for monitoring the voltage on the
VDD pin. If this voltage falls below one of selected levels, the BOD asserts an interrupt
signal to the NVIC. This signal can be enabled for interrupt in the Interrupt Enable
Register in the NVIC in order to cause a CPU interrupt; if not, software can monitor the
signal by reading a dedicated status register. Four threshold levels can be selected to
cause a forced reset of the chip.
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