參數(shù)資料
型號: LPC1316FBD48,551
廠商: NXP Semiconductors
文件頁數(shù): 47/77頁
文件大?。?/td> 0K
描述: IC MCU 32BIT 48KB FLASH 48LQFP
標準包裝: 250
系列: LPC13xx
核心處理器: ARM? Cortex?-M3
芯體尺寸: 32-位
速度: 72MHz
連通性: I²C,Microwire,SPI,SSI,SSP,UART/USART
外圍設備: 欠壓檢測/復位,POR,WDT
輸入/輸出數(shù): 40
程序存儲器容量: 48KB(48K x 8)
程序存儲器類型: 閃存
EEPROM 大小: 4K x 8
RAM 容量: 8K x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 3.6 V
數(shù)據(jù)轉換器: A/D 8x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 48-LQFP
包裝: 托盤
其它名稱: 568-9592
LPC1315_16_17_45_46_47
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 3 — 20 September 2012
51 of 77
NXP Semiconductors
LPC1315/16/17/45/46/47
32-bit ARM Cortex-M3 microcontroller
10. Dynamic characteristics
10.1 Flash/EEPROM memory
[1]
Number of program/erase cycles.
[2]
Programming times are given for writing 256 bytes from RAM to the flash. Data must be written to the flash
in blocks of 256 bytes.
10.2 External clock
[1]
Parameters are valid over operating temperature range unless otherwise specified.
[2]
Typical ratings are not guaranteed. The values listed are at room temperature (25
C), nominal supply
voltages.
Table 9.
Flash characteristics
Tamb = 40 C to +85 C, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Nendu
endurance
[1] 10000
100000
-
cycles
tret
retention time
powered
10
-
years
unpowered
20
-
years
ter
erase time
sector or multiple
consecutive sectors
95
100
105
ms
tprog
programming time
[2] 0.95
1
1.05
ms
Table 10.
EEPROM characteristics
Tamb = 40 Cto+85 C; VDD = 2.7 V to 3.6 V.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fclk
clock frequency
200
375
400
kHz
Nendu
endurance
100000
1000000
-
cycles
tret
retention time
powered
100
200
-
years
unpowered
150
300
-
years
ter
erase time
64 bytes
-
1.8
-
ms
tprog
programming
time
64 bytes
-
1.1
-
ms
Table 11.
Dynamic characteristic: external clock
Tamb = 40 C to +85 C; VDD over specified ranges.[1]
Symbol
Parameter
Conditions
Min
Typ[2]
Max
Unit
fosc
oscillator frequency
1
-
25
MHz
Tcy(clk)
clock cycle time
40
-
1000
ns
tCHCX
clock HIGH time
Tcy(clk) 0.4
-
ns
tCLCX
clock LOW time
Tcy(clk) 0.4
-
ns
tCLCH
clock rise time
-
5
ns
tCHCL
clock fall time
-
5
ns
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