參數(shù)資料
型號(hào)： LPC1315FHN33,551
廠商： NXP Semiconductors
文件頁(yè)數(shù)： 27/77頁(yè)
文件大?。?/td> 0K
描述： MCU 32BIT ARM 32KB FLASH 32HVQFN
標(biāo)準(zhǔn)包裝： 260
系列： LPC13xx
核心處理器： ARM? Cortex?-M3
芯體尺寸： 32-位
速度： 72MHz
連通性： I²C，Microwire，SPI，SSI，SSP，UART/USART
外圍設(shè)備： 欠壓檢測(cè)/復(fù)位，POR，WDT
輸入/輸出數(shù)： 28
程序存儲(chǔ)器容量： 32KB（32K x 8）
程序存儲(chǔ)器類(lèi)型： 閃存
EEPROM 大小： 2K x 8
RAM 容量： 8K x 8
電壓 - 電源 (Vcc/Vdd)： 2 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 32-VQFN 裸露焊盤(pán)
包裝： 托盤(pán)
LPC1315_16_17_45_46_47
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 3 — 20 September 2012
33 of 77
NXP Semiconductors
LPC1315/16/17/45/46/47
32-bit ARM Cortex-M3 microcontroller
Upon power-up, any chip reset, or wake-up from Deep power-down mode, the
LPC1315/16/17/45/46/47 use the IRC as the clock source. Software may later switch to
one of the other available clock sources.
7.18.1.2
System oscillator
The system oscillator can be used as the clock source for the CPU, with or without using
the PLL. On the LPC1315/16/17/45/46/47, the system oscillator must be used to provide
the clock source to USB.
The system oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be
boosted to a higher frequency, up to the maximum CPU operating frequency, by the
system PLL.
7.18.1.3
Watchdog oscillator
The watchdog oscillator can be used as a clock source that directly drives the CPU, the
watchdog timer, or the CLKOUT pin. The watchdog oscillator nominal frequency is
programmable between 9.4 kHz and 2.3 MHz. The frequency spread over processing and
temperature is
40 % (see also Table 13).
7.18.2 System PLL and USB PLL
The LPC1315/16/17/45/46/47 contain a system PLL and a dedicated PLL for generating
the 48 MHz USB clock. The system and USB PLLs are identical.
The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input
frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO).
The multiplier can be an integer value from 1 to 32. The CCO operates in the range of
156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within
its frequency range while the PLL is providing the desired output frequency. The output
divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. The PLL output
frequency must be lower than 100 MHz. Since the minimum output divider value is 2, it is
insured that the PLL output has a 50 % duty cycle. The PLL is turned off and bypassed
following a chip reset and may be enabled by software. The program must configure and
activate the PLL, wait for the PLL to lock, and then connect to the PLL as a clock source.
The PLL settling time is 100
s.
7.18.3 Clock output
The LPC1315/16/17/45/46/47 features a clock output function that routes the IRC
oscillator, the system oscillator, the watchdog oscillator, or the main clock to an output pin.
7.18.4 Wake-up process
The LPC1315/16/17/45/46/47 begin operation at power-up and when awakened from
Deep power-down mode by using the 12 MHz IRC oscillator as the clock source. This
allows chip operation to resume quickly. If the main oscillator or the PLL is needed by the
application, software will need to enable these features and wait for them to stabilize
before they are used as a clock source.
7.18.5 Power control
The LPC1315/16/17/45/46/47 support a variety of power control features. There are four
special modes of processor power reduction: Sleep mode, Deep-sleep mode,
Power-down mode, and Deep power-down mode. The CPU clock rate may also be
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