參數(shù)資料
型號: LPC1112FHN33
廠商: NXP Semiconductors N.V.
元件分類: 32位微控制器
英文描述: Cortex-M0, 16 kB flash, up to 4 kB SRAM
中文描述: Cortex-MO,16kB 閃存,最大4kB靜態(tài)隨機存儲器
封裝: LPC1112FHN33/202<SOT865-3 (HVQFN32)|<<http://www.nxp.com/packages/SOT865-3.html<1<Always Pb-free,;LPC1112FHN33/202<SOT865-3 (HVQFN32)|<<http://www.nxp.com/packages/SOT865
文件頁數(shù): 6/12頁
文件大?。?/td> 89K
代理商: LPC1112FHN33
NXP Semiconductors
AN10960
DALI slave using the LPC1112
AN10960
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Application note
Rev. 1 — 22 July 2010
6 of 12
via preheat- and ignition phase (if applicable). During the 100 ms interval the ballast shall
react on a possible command if this ‘POWER-ON LEVEL’ is not desired.
Logarithmic Dimming Curve
The lowest dimming level of the ballast is 0.1 % and is coupled to the digital value ‘1’ in
the range of 1 to 254 (absolute dimming). The highest arc power level of the ballast
(100 %) is coupled to the digital value ‘254’. A logarithmic dimming curve from 0.1 % to
100 % is defined (see
Fig 2
). Because of the many different influences, dim levels can
only have the meaning of arc power level of a lamp.
Fig 2.
Example of a logarithmic dimming curve
Min and Max Control Level
Programming a MIN level above or a MAX level below the actual power level will set the
actual power level to the new MIN level or MAX level. Programming a MIN level below or
a MAX level above the actual power level will not affect the actual arc power level.
A required level below the MIN level or above the MAX level will cause the ballast to
operate at MIN LEVEL or MAX LEVEL.
The arc power levels ‘0’ (OFF) and ‘255’ (MASK) shall not be affected by the MIN and
MAX LEVEL settings.
0
10
20
30
40
50
60
70
80
90
100
1
1
2
3
4
5
6
7
8
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
8-bit control level
"
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