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參數(shù)資料
| 型號： | LP722 |
| 廠商： | Polyfet RF Devices |
| 英文描述： | SILICON GATE ENHANCEMENT MODE RF POWER LDMOS TRANSISTOR |
| 中文描述： | 硅柵增強型射頻功率LDMOS晶體管 |
| 文件頁數(shù)： | 1/2頁 |
| 文件大?。?/td> | 35K |
| 代理商： | LP722 |
polyfet rf devices
LP722
10
Single Ended
AP
80.0
4.0
100.0
1.00 C/W
40
3.4
26.00
4.0
55
0.30
12.00
15.0
150
0.40
50
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
TEST CONDITIONS
Common Source Power Gain
Drain Efficiency
Total
Device
Dissipation
Junction to
Case Thermal
Resistance
Maximum
Junction
Temperature
Storage
Temperature
DC Drain
Current
Drain to
Source
Voltage
Gate to
Source
Voltage
-65 C to 150 C
200 C
A
V
Load Mismatch Tolerance
VSWR
Drain to
Gate
Voltage
20:1
Relative
0.40
0.40
Ids =
mA, Vgs = 0V
V, Vgs = 0V
Ciss
Crss
Coss
Vds =
Idq =
A, Vds = V, F =
0.40
Bvdss
Idss
Drain Breakdown Voltage
V
mA
pF
pF
pF
Common Source Output Capacitance
Common Source Feedback Capacitance
Idq =
Idq = 0.40
500
Vgs = 20V, Ids =
Rdson
Saturation Resistance
Forward Transconductance
gM
Vds = 10V, Vgs = 5V
POLYFET RF DEVICES
1110 Avenida Acaso, Camarillo, Ca 93012 Tel:(805) 484-4210 FAX: (805) 484-3393 EMAIL:Sales@polyfet.com URL:www.polyfet.com
500
500
Common Source Input Capacitance
50
V
20
Igss
Vgs
Idsat
Zero Bias Drain Current
Gate Leakage Current
Gate Bias for Drain Current
Saturation Current
1
7
uA
V
Mho
Ohm
Amp
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
TEST CONDITIONS
ELECTRICAL CHARACTERISTICS ( EACH SIDE )
RF CHARACTERISTICS (
35.0
ABSOLUTE MAXIMUM RATINGS ( T =
Gps
A, Vds = V, F =
A, Vds = V, F =
Watts
V
1
MHz
MHz
MHz
Watts
Package Style
35.0
Vds = 0V Vgs = 30V
Vgs = 20V, Vds = 10V
HIGH EFFICIENCY, LINEAR
HIGH GAIN, LOW NOISE
General Description
Silicon VDMOS and LDMOS
transistors designed specifically
for broadband RF applications.
Suitable for Militry Radios,
Cellular and Paging Amplifier Base
Stations, Broadcast FM/AM, MRI,
Laser Driver and others.
12.5
Vds =
A, Vgs = Vds
Ids =
A
η
dB
%
o
o
o
"Polyfet" process features
low feedback and output capacitances
resulting in high F transistors with high
input impedance and high efficiency.
SILICON GATE ENHANCEMENT MODE
RF POWER
TRANSISTOR
LDMOS
Vgs = 0V, F = 1 MHz
12.5
Vds =
Vgs = 0V, F = 1 MHz
12.5
Vds =
Vgs = 0V, F = 1 MHz
12.5
REVISION 04/30/2001
25 C )
WATTS OUTPUT )
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