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參數(shù)資料
| 型號： | LP62P16128CU-12LLT |
| 廠商： | AMIC Technology Corporation |
| 元件分類： | SRAM |
| 英文描述： | 128K X 16 BIT LOW VOLTAGE CMOS SRAM |
| 中文描述： | 128K的× 16位低電壓CMOS的SRAM |
| 文件頁數(shù)： | 13/15頁 |
| 文件大?。?/td> | 163K |
| 代理商： | LP62P16128CU-12LLT |
LP62P16128C-T Series
PRELIMINARY
(March, 2002, Version 0.0)
6
AMIC Technology, Inc.
AC Characteristics (TA = -25
°C to +85°C, VCC = 2.3V to 2.7V)
Symbol
Parameter
LP62P16128C-12LLT
Unit
Min.
Max.
Read Cycle
tRC
Read Cycle Time
120
-
ns
tAA
Address Access Time
-
120
ns
tACE
Chip Enable Access Time
-
120
ns
tBE
Byte Enable Access Time
-
120
ns
tOE
Output Enable to Output Valid
-
80
ns
tCLZ
Chip Enable to Output in Low Z
10
-
ns
tBLZ
Byte Enable to Output in Low Z
10
-
ns
tOLZ
Output Enable to Output in Low Z
5
-
ns
tCHZ
Chip Disable to Output in High Z
-
45
ns
tBHZ
Byte Disable to Output in High Z
-
45
ns
tOHZ
Output Disable to Output in High Z
-
45
ns
tOH
Output Hold from Address Change
10
-
ns
Write Cycle
tWC
Write Cycle Time
120
-
ns
tCW
Chip Enable to End of Write
100
-
ns
tBW
Byte Enable to End of Write
100
-
ns
tAS
Address Setup Time
0
-
ns
tAW
Address Valid to End of Write
100
-
ns
tWP
Write Pulse Width
85
-
ns
tWR
Write Recovery Time
0
-
ns
tWHZ
Write to Output in High Z
-
35
ns
tDW
Data to Write Time Overlap
60
-
ns
tDH
Data Hold from Write Time
0
-
ns
tOW
Output Active from End of Write
10
-
ns
Note: tBLZ, tOLZ, tCHZ, tBHZ and tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit condition
and are not referred to output voltage levels.
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| LP62P16128CV-12LLT | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:128K X 16 BIT LOW VOLTAGE CMOS SRAM |
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| LP62S1024AM-55LLT | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:128K X 8 BIT LOW VOLTAGE CMOS SRAM |
| LP62S1024AM-70LLT | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:128K X 8 BIT LOW VOLTAGE CMOS SRAM |
| LP62S1024A-T | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:128K X 8 BIT LOW VOLTAGE CMOS SRAM |
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