- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄358908 > LP2975IMM-12 (NATIONAL SEMICONDUCTOR CORP) MOSFET LDO Driver/Controller PDF資料下載
參數(shù)資料
| 型號： | LP2975IMM-12 |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | MOSFET LDO Driver/Controller |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDSO8 |
| 封裝： | MINI, SOP-8 |
| 文件頁數(shù)： | 17/19頁 |
| 文件大?。?/td> | 715K |
| 代理商： | LP2975IMM-12 |
Application Hints
(Continued)
This application can also be improved by adding a feed-
forward capacitor. C
will add both a zero f
and pole f
to
the gain plot (see graph LOW ESR CORRECTED WITH
FEED-FORWARD).
The crossover frequency f
is now about 10 kHz. If C
is se-
lected so that f
zf
is about 5 kHz, and f
is about 20 kHz
(which means V
= 5V), the phase margin will be consid-
erably improved. Calculating out all the poles and zeroes,
the phase margin is increased from 9 to 43 (adequate for
good stability).
EXCESSIVE GATE CAPACITANCE
: Higher values of gate
capacitance shift the pole f
to lower frequencies, which can
cause stability problems (see previous section GATE CA-
PACITANCE POLE FREQUENCY). As shown in the graph
f
vs. C
, the pole f
will likely fall somewhere between
40 kHz and 500 kHz. How much phase shift this adds de-
pends on the crossover frequency f
c
.
The effect of gate capacitance becomes most important at
high values of ESR for the output capacitor (see graph HIGH
ESR UNSTABLE WITHOUT FEED-FORWARD). Higher val-
ues of ESR increase f
, which brings f
more into the posi-
tive gain portion of the curve. As f
moves to a lower fre-
quency
(corresponding
to
capacitance), this effect becomes even worse.
This points out why FET’s should be selected with the lowest
possible gate capacitance: it makes the design more tolerant
of higher ESR values on the output capacitor.
higher
values
of
gate
The use of a feed-forward capacitor C
will help reduce ex-
cess phase shift due to f
, but its effectiveness depends on
output voltage (see next section).
LOW OUTPUT VOLTAGE AND C
F
The feed-forward capacitor C
will provide a positive phase
shift (lead) which can be used to cancel some of the excess
phase lag from any of the various poles present in the loop.
However, it is important to note that the effectiveness of C
F
decreases with output voltage.
This is due to the fact that the frequencies of the zero f
and
pole f
get closer together as the output voltage is reduced
(see equations in section FEED-FORWARD COMPENSA-
TION).
C
is more effective when the pole-zero pair are farther
apart, because there is less self cancellation. The net benefit
in phase shift provided by C
is the
difference
between the
lead (positive phase shift) from f
and the lag (negative
phase shift) from f
which is present at the crossover fre-
quency f
. As the pole and zero frequency approach each
other, that difference diminishes to nothing.
The amount of phase lead at f
provided by C
depends
both on the f
f
ratio and the location of f
with respect to f
c
.
To illustrate this more clearly, a graph is provided which
shows how much phase lead can be obtained for V
=
12V, 5V, and 3.3V (see graph PHASE LEAD PROVIDED BY
C
F
).
The most important information on the graph is the fre-
quency range of f
which will provide the maximum benefit
(most positive phase shift):
For V
OUT
= 12V: 0.1 f
c
<
f
z
<
1.0 f
c
For V
OUT
= 5V: 0.2 f
c
<
f
z
<
1.2 f
c
For V
OUT
= 3.3V: 0.2 f
c
<
f
z
<
1.3 f
c
It’s also important to note how the maximum available phase
shift that C
can provide drops off with V
. At 12V, more
than 50 can be obtained, but at 3.3V less than 30 is pos-
sible. The lesson from this is that higher voltage designs are
more tolerant of phase shifts from both f
pg
(the gate capaci-
tance pole) and incorrect placement of f
(which means the
output capacitor ESR is not at its nominal value). At lower
values of V
, these parameters must be more precisely
selected since C
F
can not provide as much correction.
GENERAL DESIGN PROCEDURE
Assuming that V
IN
, V
OUT
, and R
L
are defined:
Low ESR Unstable without Feed-Forward
DS100034-30
Low ESR Corrected with Feed-Forward
DS100034-32
Phase Lead Provided by C
F
DS100034-33
www.national.com
17
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LP2975 | Quadruple 2-Input Exclusive-OR Gates 14-SOIC -40 to 85 |
| LP2978 | Micropower SOT, 50 mA Low-Noise Ultra Low-Dropout Regulator |
| LP2978AIM5-3.8 | Micropower SOT, 50 mA Low-Noise Ultra Low-Dropout Regulator |
| LP2978AIM5X-3.8 | SUBMINIATURE PC BOARD RELAY |
| LP2978IM5-3.8 | SUBMINIATURE PC BOARD RELAY |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LP2975IMM-12/NOPB | 功能描述:IC REG CTRLR SGL 12V 8-MSOP RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - 線性晶體管驅(qū)動(dòng)器 系列:- 產(chǎn)品培訓(xùn)模塊:More Information on LDOs 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:正，固定式 輸出數(shù):2 輸出電壓:2.8V，3.3V 電流 - 電源:12mA 輸入電壓:5 V ~ 22 V 工作溫度:0°C ~ 70°C 封裝/外殼:16-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
| LP2975IMM-3.3 | 功能描述:低壓差穩(wěn)壓器 - LDO RoHS:否 制造商:Texas Instruments 最大輸入電壓:36 V 輸出電壓:1.4 V to 20.5 V 回動(dòng)電壓（最大值）:307 mV 輸出電流:1 A 負(fù)載調(diào)節(jié):0.3 % 輸出端數(shù)量: 輸出類型:Fixed 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-20 |
| LP2975IMM-3.3/NOPB | 功能描述:低壓差穩(wěn)壓器 - LDO RoHS:否 制造商:Texas Instruments 最大輸入電壓:36 V 輸出電壓:1.4 V to 20.5 V 回動(dòng)電壓（最大值）:307 mV 輸出電流:1 A 負(fù)載調(diào)節(jié):0.3 % 輸出端數(shù)量: 輸出類型:Fixed 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-20 |
| LP2975IMM-5.0 | 功能描述:低壓差穩(wěn)壓器 - LDO RoHS:否 制造商:Texas Instruments 最大輸入電壓:36 V 輸出電壓:1.4 V to 20.5 V 回動(dòng)電壓（最大值）:307 mV 輸出電流:1 A 負(fù)載調(diào)節(jié):0.3 % 輸出端數(shù)量: 輸出類型:Fixed 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-20 |
| LP2975IMM-5.0/NOPB | 功能描述:低壓差穩(wěn)壓器 - LDO RoHS:否 制造商:Texas Instruments 最大輸入電壓:36 V 輸出電壓:1.4 V to 20.5 V 回動(dòng)電壓（最大值）:307 mV 輸出電流:1 A 負(fù)載調(diào)節(jié):0.3 % 輸出端數(shù)量: 輸出類型:Fixed 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-20 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。