參數(shù)資料
型號(hào): LP2950-33LP
廠商: Texas Instruments, Inc.
英文描述: ADJUSTABLE MICROPOWER VOLTAGE REGULATORS WITH SHUTDOWN
中文描述: 可調(diào)微功耗電壓調(diào)節(jié)器具有關(guān)斷
文件頁(yè)數(shù): 15/26頁(yè)
文件大?。?/td> 2721K
代理商: LP2950-33LP
www.ti.com
APPLICATION INFORMATION
Input Capacitor (C
IN
)
A 1-
μ
F (tantalum, ceramic, or aluminum) electrolytic capacitor should be placed locally at the input of the
LP2950 or LP2951 if there is, or will be, significant impedance between the ac filter capacitor and the input; for
example, if a battery is used as the input or if the ac filter capacitor is located more than 10 in away. There are
no ESR requirements for this capacitor, and the capacitance can be increased without limit.
Output Capacitor (C
OUT
)
As with most PNP LDOs, stability conditions require the output capacitor to have a minimum capacitance and an
ESR that falls within a certain range.
Capacitance Value
For V
5 V, a minimum of 1
μ
F is required. For lower V
, the regulator’s loop gain is running closer to
unity gain and, thus, has lower phase margins. Consequently, a larger capacitance is needed for stability. For
V
OUT
= 3 V or 3.3 V, a minimum of 2.2
μ
F is recommended. For worst case, V
OUT
= 1.23 V (using the ADJ
version), a minimum of 3.3
μ
F is recommended. C
can be increased without limit and only improves the
regulator stability and transient response. Regardless of its value, the output capacitor should have a resonant
frequency less than 500 kHz.
ESR Range
The regulator control loop relies on the ESR of the output capacitor to provide a zero to add sufficient phase
margin to ensure unconditional regulator stability; this requires the closed-loop gain to intersect the open-loop
response in a region where the open-loop gain rolls off at 20 dB/decade. This ensures that the phase always is
less than 180
°
(phase margin greater than 0
°
) at unity gain. Thus, a minimum-maximum range for the ESR must
be observed.
LP2950
,
LP2951
ADJUSTABLE MICROPOWER VOLTAGE REGULATORS
WITH SHUTDOWN
SLVS582D–APRIL 2006–REVISED MARCH 2007
The minimum capacitance values given above are for maximum load current of 100 mA. If the maximum
expected load current is less than 100 mA, then lower values of C
OUT
can be used. For instance, if I
OUT
< 10
mA, then only 0.33
μ
F is required for C
OUT
. For I
OUT
< 1 mA, 0.1
μ
F is sufficient for stability requirements. Thus,
for a worst-case condition of 100-mA load and V
= V
= 1.235 V (representing the highest load current and
lowest loop gain), a minimum C
OUT
of 3.3
μ
F is recommended.
For the LP2950, no load stability is inherent in the design — a desirable feature in CMOS circuits that are put in
standby (such as RAM keep-alive applications). If the LP2951 is used with external resistors to set the output
voltage, a minimum load current of 1
μ
A is recommended through the resistor divider.
The upper limit of this ESR range is established by the fact that too high an ESR could result in the zero
occurring too soon, causing the gain to roll off too slowly, which, in turn allows a third pole to appear before unity
gain and introduce enough phase shift to cause instability. This typically limits the max ESR to approximately
5
.
Conversely, the lower limit of the ESR is tied to the fact that too low an ESR shifts the zero too far out (past
unity gain) and, thus, allows the gain to roll off at 40 dB/decade at unity gain, with a resulting phase shift of
greater than 180
°
. Typically, this limits the minimum ESR to approximately 20 m
to 30 m
.
For specific ESR requirements, see
Typical Characteristics
.
15
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