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參數(shù)資料
| 型號(hào)： | LOAD |
| 英文描述： | Load Balance Controller. EZ1900 and Low-Dropout Regulators (35k) |
| 中文描述： | 負(fù)載平衡控制器。 EZ1900和低壓差穩(wěn)壓器（為35K） |
| 文件頁數(shù)： | 1/3頁 |
| 文件大小： | 36K |
| 代理商： | LOAD |
AN96-5
Load Balance Controller, EZ1900 and
LP2951 + StP8 Regulator
2000 SEMTECH CORP.
652 MITCHELL ROAD NEWBURY PARK CA 91320
August 28, 2000
1
Using the Load Balance Controller, EZ1900, with an LP2951 & StP8
Combination Regulator for a Flexible Motherboard Design
Introduction
The EZ1900 load balance controller is a flexible, low
cost device, providing an automatic power supply up-
grade from single to split-voltage plane processors,
when used with two low dropout regulators. Single
plane processors, such as the Intel Pentium
Proces-
sor P54C, Cyrix 6x86, AMD AMD5
86 and the
PowerPC require a single supply voltage, normally
3.3 or 3.5V.
New split plane processors, such as the Pentium P55C
and versions of the 6x86, AMD5
K
86 & PowerPC
603/604EV require two supply voltages: V
I/O
for the I/O
circuitry, at 3.3 or 3.5V; and V
CC2
for the CPU core, at
between 2.5 and 2.8V.
The EZ1900 can be used with almost any type of
voltage regulator. Application note AN96-4 describes
how to use the EZ1900 with a three- or five-terminal low
dropout regulator. This application note describes how
to use the EZ1900 with Semtech’s low cost LP2951 &
StP8 discrete regulator combination to provide an auto-
matic upgrade path, avoiding costly production
changes or jumpers for different processors.
Principle of Operation
In split plane operation, the EZ1900 switches the output
of the slave regulator to the higher voltage required for
I/O .
When operating in single plane mode, the EZ1900
controls the output of the slave regulator to provide a
lower voltage for V
, sharing current with the master
for processors whose I/O and core power planes are
connected together. In this mode the two regulators’
operate as master and slave.
Microprocessors, such as those listed above, have a
pin, V
, or similar, which, indicates to the EZ1900
in which mode to operate. Pin 1 (SEL) of the EZ1900
detects this signal: floating (or open)
indicates single-plane (current shar-
ing) and low switches the outputs for
split-plane operation.
A typical application circuit is shown in
figure 1. The master regulator powers
the CPU core and the slave supplies
the I/O circuitry.
Current Sharing
The EZ1900 controls current sharing
by sensing the input current to the two
regulators by means of the two sense
resistors, R
15
& R
14
. For balanced cur-
rents, the voltage drop across each
resistor should be of the order of 50 -
100mV [around 10 - 20m
=
for a 5A
current].
For most split-plane regulators, the
CPU core requires no more than 6A,
with 3A or less for the I/O. The two
regulators will provide enough power
in master-slave mode to power all
versions of the Cyrix 6x86 processor
at 8A or more.
Pentium is a registered trademark of Intel Corporation; 6x86 is a trademark of Cyrix Corporation; AMD5
K
86 is a trademark of
AMD; PowerPC is a trademark of IBM.
VIN
VCC2
VIN
VIO
MASTER
LP2951CM
SLAVE
C1
+
R3
33
R1
390
C2
+
R8
15k
C5
0.1uF
C6
+
R12
33
R9
390
C10
0.1uF
C7
0.1uF
(R4
Q2
STP8
Q3
STP8
(R11
C9
470uF/16V
+
C3
0.1uF
U3
EZ1900
+V
7
SEL
1
+IN
3
SOUT
6
-V
4
-IN
2
R13
15k
R15
(See Table1)
R14 (See Table1)
U1
OUTPUT
1
SENSE
2
SHUTDOWN
3
GROUND
4
ERROR
5
5V TAP
6
FEEDBACK
7
INPUT
8
U2
LP2951CM
OUTPUT
1
SENSE
2
SHUTDOWN
3
GROUND
4
ERROR
5
5V TAP
6
FEEDBACK
7
INPUT
8
MODE
Figure 1: Typical Application Circuit
TEL:805-498-2111 FAX:805-498-3804 WEB:http://www.semtech.com
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