參數(shù)資料
型號: LNK574DG
廠商: POWER INTEGRATIONS INC
元件分類: 模擬信號調(diào)理
英文描述: SPECIALTY ANALOG CIRCUIT, PDSO8
封裝: GREEN, PLASTIC, MS-012, SOP-8
文件頁數(shù): 10/16頁
文件大?。?/td> 1515K
代理商: LNK574DG
Rev. B 12/07/10
3
LNK574
www.powerint.com
LinkZero-LP Functional Description
LinkZero-LP comprises a 700 V power MOSFET switch with a
power supply controller on the same die. Unlike conventional
PWM (pulse width modulation) controllers, it uses a simple ON/
OFF control to regulate the output voltage. The controller
consists of the following circuits, an oscillator, feedback (sense)
5.85 V regulator, BYPASS pin under/overvoltage protection,
over-temperature protection, frequency jittering, current limit,
leading edge blanking BYPASS pin clamp in power down and
bypass mode. The controller includes a proprietary power
down mode that automatically reduces standby consumption to
levels that are immeasurable on most power meters.
Power Down Mode
The device enters into power down mode (where MOSFET
switching is disabled) when the total load (power supply output
plus bias winding loads) has reduced to ~0.6% of full load. The
internal controller detects this condition by sensing when 160
cycles have been skipped twice with only one active switching
cycle in between the two sets of 160 skipped switching cycles.
During the power down period the BYPASS pin capacitor will
discharge from 5.85 V down to about 3 V at which point the
LinkZero-LP will wake up and charge the BYPASS pin back up
to 5.85 V. The wake up frequency is determined by the user
through the choice of the BYPASS pin capacitor value (see
Figure 22 for BYPASS pin capacitor choice). Once the BYPASS
pin has recharged 5.85 V LinkZero-LP senses if the load
condition has changed or not, if not the LinkZero-LP will enter
into a new power down cycle or otherwise resumes normal
operation (See Applications Example section for more details of
power down mode operation).
Oscillator
The typical oscillator frequency is internally set to an average of
100 kHz. An internal circuit senses the on-time of the MOSFET
switch and adjusts the oscillator frequency so that at large duty
cycle (low line voltage) the frequency is about 100 kHz and at
small duty cycle (high line voltage) the oscillator frequency is
about 78 kHz. This internal frequency adjustment is used to
make the peak power point constant over line voltage. Two
signals are generated from the oscillator: the maximum duty
cycle signal (DC
MAX) and the clock signal that indicates the
beginning of a switching cycle.
The oscillator incorporates circuitry that introduces a small
amount of frequency jitter, typically 6% of the switching frequency,
to minimize EMI. The modulation rate of the frequency jitter is
set to 1 kHz to optimize EMI reduction for both average and
quasi-peak emissions. The frequency jitter, which is proportional
to the oscillator frequency, should be measured with the
oscilloscope triggered at the falling edge of the drain voltage
waveform. The oscillator frequency is linearly reduced when the
FEEDBACK pin voltage is lowered from 1.70 V down to 1.37 V.
Feedback Input Circuit CV Mode
The feedback input circuit reference is set at 1.70 V at full load
and gradually reduces down to 1.37 V at no-load. When the
FEEDBACK pin voltage reaches a V
FB reference voltage (1.70 V
to 1.37 V) depending on the load, a low logic level (disable) is
generated at the output of the feedback circuit. This output is
sampled at the beginning of each cycle. If high, the power
MOSFET is turned on for that cycle (enabled), otherwise the
power MOSFET remains off (disabled). Since the sampling is
done only at the beginning of each cycle, subsequent changes
in the FEEDBACK pin voltage during the remainder of the cycle
are ignored.
Feedback Input CC Mode
When the FEEDBACK pin voltage at full load falls below 1.70 V,
the oscillator frequency linearly reduces to typically 43% at the
auto-restart threshold voltage of 0.9 V. This function limits the
power supply output power at output voltages below the rated
voltage regulation threshold V
R (see Figure 1).
5.85 V Regulator
The BYPASS pin voltage is regulated by drawing a current from
the DRAIN whenever the MOSFET is off if needed to charge up
the BYPASS pin to a typical voltage of 5.85 V. When the
MOSFET is on, LinkZero-LP runs off of the energy stored in the
bypass capacitor. Extremely low power consumption of the
internal circuitry allows LinkZero-LP to operate continuously
from the current drawn from the DRAIN pin. A bypass
capacitor value of 0.1
mF is sufficient for both high frequency
decoupling and energy storage.
6.5 V Shunt Regulator and 8.5 V Clamp
In addition, there is a shunt regulator that helps maintain the
BYPASS pin at 6.5 V when current is provided to the BYPASS
pin externally. This facilitates powering the device externally
through a resistor from the bias winding or power supply output
in non-isolated designs, to decrease device dissipation and
increase power supply efficiency.
The 6.5 V shunt regulator is only active in normal operation, and
when in power down mode a clamp at a higher voltage (typical
8.5 V) will clamp the BYPASS pin.
BYPASS Pin Undervoltage Protection
The BYPASS pin undervoltage circuitry disables the power
MOSFET when the BYPASS pin voltage drops below 4.85 V.
Once the BYPASS pin voltage drops below 4.85 V, it must rise
back to 5.85 V to enable (turn on) the power MOSFET.
BYPASS Pin Overvoltage Protection
If the BYPASS pin gets pulled above 6.5 V (BP
SHUNT)and the
current into the shunt exceeds 6.5 mA a latch will be set and
the power MOSFET will stop switching. To reset the latch the
BYPASS pin has to be pulled down to below 1.5 V.
Over-Temperature Protection
The thermal shutdown circuit senses the die temperature. The
threshold is set at 142
°C typical with a 70 °C hysteresis. When
the die temperature rises above this threshold (142
°C) the power
MOSFET is disabled and remains disabled until the die temperature
falls by 70
°C, at which point the MOSFET is re-enabled.
Current Limit
The current limit circuit senses the current in the power MOSFET.
When this current exceeds the internal threshold (I
LIMIT), the
power MOSFET is turned off for the remaining of that cycle.
The leading edge blanking circuit inhibits the current limit
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