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參數(shù)資料
| 型號： | LMX9402 |
| 文件頁數(shù)： | 2/7頁 |
| 文件大小： | 152K |
| 代理商： | LMX9402 |
Connection Diagram
Pin Descriptions
Pin No.
Pin
Name
GND
LD
I/O
Description
1,2,3,4,5
6
—
O
Ground.
Multiplexed output of the RF programmable dividers, reference dividers, or RF Lock
Detect. Normally used as RF Lock Detect.
Ground.
Power supply voltage input to PLL.
Ground.
VCO Frequency Output.
Ground.
Power supply voltage input to VCO
Ground.
7
8
9
10
GND
V
CC1
GND
RFOUT
GND
V
CC2
GND
—
—
—
O
—
—
—
11, 12
13
14, 15,
16
17
Data
I
Binary serial data input. Data entered MSB first. LSB is control bit. High impedance
CMOS input.
Ground.
18, 19,
20
21
22
GND
—
OSC
IN
CLK
I
I
Reference Oscillator input.
High impedance CMOS Clock input. Data is clocked in on the rising edge, into the
various counters and registers.
Load Enable input (with internal pull-up resistor). When LE Load Enable transitions
HIGH, data stored in the shift registers is loaded into the appropriate latch (control bit
dependent). Clock must be low when LE toggles high or low.
Ground.
23
LE
I
24, 25
GND
—
DS200075-2
Top View 25-Pin CBGA Package
See NS Package Number SB25A
L
www.national.com
2
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