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參數(shù)資料
| 型號(hào)： | LMX2532LQX1065 |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | PLLatinum Frequency Synthesizer System with Integrated VCOs |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 19.68 MHz, QCC28 |
| 封裝： | 5 X 5 MM, 0.75 MM HEIGHT, LLP-28 |
| 文件頁(yè)數(shù)： | 16/18頁(yè) |
| 文件大?。?/td> | 189K |
| 代理商： | LMX2532LQX1065 |
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Programming Description
(Continued)
R4 REGISTER
The R4 register address bits (R3 [3:0]) are “0111”.
Register R4 is used to set the IF N counters if the default value is not desired. This register is only active if the SPI_DEF bit in
register R0 is 0.
The IF N counter consists of the 9-bit programmable counter (IF_B counter) and the 4-bit swallow counter (IF_A counter). The
equations for calculating the counter values are presented below.
R4 REGISTER
R
MSB
23
SHIFT REGISTER BIT LOCATION
16
15
14
13
Data Field
LSB
0
22
21
20
19
18
17
12
11
10
9
8
7
6
5
4
3
2
Address
Field
1
1
1
R4
0
0
0
1
0
0
0
IF_A
[3:0]
IF_B
[8:0]
0
1
Name
IF_A [3:0]
Functions
IF A Counter
4-bit swallow counter
0
≤
IF_A
≤
15
IF B Counter
9-bit programmable counter
1
≤
IF_B
≤
511
IF_B [8:0]
IF Frequency Setting:
f
VCO
= {16 x IF_B + IF_A} x f
OSC
/ R where (IF_A
<
IF_B)
where
f
VCO
: Output frequency of IF voltage controlled oscillator (IF VCO)
IF_B: Preset divide ratio of binary 9-bit programmable counter (1
≤
IF_B
≤
511)
IF_A: Preset divide ratio of binary 4-bit swallow counter (0
≤
IF_A
≤
15)
IF_R: Preset divide ratio of binary 9-bit programmable reference counter (2
≤
IF_R
≤
511)
f
OSC
: Reference oscillator frequency
R5 REGISTER
The R5 register address bits (R5 [4:0]) are “01111”.
Register R5 is used to set the IF_R divider if the default value is not desired. This register is only active if the SPI_DEF bit in
register R0 is 0.
R5 REGISTER
R
MSB
23
SHIFT REGISTER BIT LOCATION
16
15
14
13
Data Field
LSB
0
22
21
20
19
18
17
12
11
10
9
8
7
6
5
4
3
2
1
Address
Field
1
R5
0
0
1
1
0
0
0
0
1
0
IF_R
[8:0]
0
1
1
1
Name
IF_R [8:0]
Functions
IF R Counter
9-bit programmable counter
2
≤
IF_R
≤
511
L
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