- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄358887 > LMX2532LQ0967 (NATIONAL SEMICONDUCTOR CORP) PLLatinum Frequency Synthesizer System with Integrated VCOs PDF資料下載
參數(shù)資料
| 型號(hào)： | LMX2532LQ0967 |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | PLLatinum Frequency Synthesizer System with Integrated VCOs |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 19.68 MHz, QCC28 |
| 封裝： | 5 X 5 MM, 0.75 MM HEIGHT, LLP-28 |
| 文件頁(yè)數(shù)： | 15/18頁(yè) |
| 文件大小： | 189K |
| 代理商： | LMX2532LQ0967 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)當(dāng)前第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)
Programming Description
(Continued)
R3 REGISTER
The R3 register address bits (R3 [2:0]) are “011”.
Register R3 contains the controls for the phase lock bandwidth controls (BW_DUR, BW_CRL and BW_EN). The duration of the
digital controller portion of the bandwidth control is set by BW_DUR [1:0]. The minimum time set with 00 and increasing durations
to the maximum value set with 11. BW_CRL [1:0] sets the phase offset criterion for the bandwidth controller. Once the phase
offset between the reference clock and the divided VCO signal are within the set criterion, the bandwidth control stops. The
maximum phase offset is set with 00 and decreases to the minimum value set with 11. BW_EN enables the bandwidth control in
the locking state.
The VCO dynamic current is also controlled in register R3 with VCO_CUR [1:0]. The minimum value corresponds to 00 and
increases to a maximum value set at 11.
R3 REGISTER
R
MSB
23
SHIFT REGISTER BIT LOCATION
16
15
14
13
Data Field
LSB
0
22
21
20
19
18
17
12
11
10
9
8
7
6
5
4
3
2
1
Address
Field
1
R3
(Default)
BW_
DUR
[1:0]
BW_
CRL
[1:0]
BW_
EN
1
0
1
1
1
1
0
1
0
0
0
1
1
0
VCO_
CUR
[1:0]
0
1
Name
BW_DUR [1:0]
Functions
Bandwidth Duration
00 = Minimum value (Recommended)
01 =
10 =
11 = Maximum value
Bandwidth Control
00 = Maximum phase offset (Recommended)
01 =
10 =
11 = Minimum phase offset
Bandwidth Enable
0 = Disable
1 = Enable (Recommended)
VCO Dynamic Current
00 = Minimum value
01 =
10 =
11 = Maximum value (Recommended)
BW_CRL [1:0]
BW_EN
VCO_CUR [1:0]
L
www.national.com
15
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LMX2532 | PLLatinum Frequency Synthesizer System with Integrated VCOs |
| LMX2542LQ2121 | PLLatinum Cellular and GPS Frequency Synthesizer System with Integrated VCO |
| LMX2542LQX2121 | PLLatinum Cellular and GPS Frequency Synthesizer System with Integrated VCO |
| LMX2542 | PLLatinum Cellular and GPS Frequency Synthesizer System with Integrated VCO |
| LMX2604 | Triple-band VCO for GSM900/DCS1800/PCS1900 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LMX2532LQ0967/NOPB | 功能描述:IC FREQ SYNTH DUAL W/VCO 28LLP RoHS:是 類別:RF/IF 和 RFID >> RF 其它 IC 和模塊 系列:PLLatinum™ 標(biāo)準(zhǔn)包裝:100 系列:* |
| LMX2532LQ1065 | 制造商:Rochester Electronics LLC 功能描述:PLL+VCO CDMA+GPS - Bulk 制造商:Texas Instruments 功能描述:IC PLL VCO SMD 2532 LLP-28 |
| LMX2532LQ1065/NOPB | 功能描述:IC FREQ SYNTH DUAL W/VCO 28LLP RoHS:是 類別:RF/IF 和 RFID >> RF 其它 IC 和模塊 系列:PLLatinum™ 標(biāo)準(zhǔn)包裝:100 系列:* |
| LMX2532LQX0967 | 功能描述:IC SYNTHESIZER PLL VCO GPS 28LLP RoHS:是 類別:RF/IF 和 RFID >> RF 其它 IC 和模塊 系列:PLLatinum™ 標(biāo)準(zhǔn)包裝:100 系列:* |
| LMX2532LQX1065 | 功能描述:IC SYNTHESIZER PLL VCO GPS 28LLP RoHS:是 類別:RF/IF 和 RFID >> RF 其它 IC 和模塊 系列:PLLatinum™ 標(biāo)準(zhǔn)包裝:100 系列:* |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。