參數(shù)資料
型號: LMX2531LQ2570E
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: XO, clock
英文描述: PLLatinum High Performance Frequency Synthesizer System with Integrated VCO
中文描述: PLL FREQUENCY SYNTHESIZER, 80 MHz, QCC36
封裝: 6 X 6 MM, 0.80 MM HEIGHT, LEAD FREE, LLP-36
文件頁數(shù): 23/25頁
文件大小: 589K
代理商: LMX2531LQ2570E
2.0 General Programming Information
(Continued)
2.10 REGISTERS R9 and R12
2.10.1 LDDIV4- RF Digital Lock Detect Divide By 4
Because the digital lock detect function is based on a phase error, it becomes more difficult to detect a locked condition for larger
comparison frequencies. When this bit is enabled, it subdivides the RF PLL comparison frequency presented to the digital lock
detect circuitry by 4. This enables this circuitry to work at higher comparison frequencies. It is recommended that this bit be
enabled whenever the comparison frequency exceeds 20 MHz and RF digital lock detect is used. This does not apply to the IF
comparison frequency.
2.11 REGISTER R12
This register does not have user selectable bits. This register should be loaded as shown in section 2.02 Complete Register
Content Map.
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