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參數(shù)資料
| 型號： | LMX2525LQX1321 |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | PLLatinum Dual Frequency Synthesizer System with Integrated VCOs |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 26 MHz, QCC24 |
| 封裝： | 5 X 4 MM, 0.75 MM HEIGHT, LLP-24 |
| 文件頁數(shù)： | 9/17頁 |
| 文件大?。?/td> | 237K |
| 代理商： | LMX2525LQX1321 |
Functional Description
GENERAL
The LMX2525 is a highly integrated frequency synthesizer
system for Japan PDC wireless communication systems.
The LMX2525 supports dual band operation for 800 MHz
and 1500 MHz.
The LMX2525 includes all functional blocks for the RF PLL
including RF VCOs, frequency dividers, PFDs, and loop
filters. Only external passive elements for the RF2 VCO tank
and supply bypassing are required to complete the RF syn-
thesizer.
The LMX2525 uses a patent pending Fractional-N synthe-
sizer architecture based on a delta sigma modulator to sup-
port fine frequency resolution. Four of the most common
reference frequencies for PDC applications, 12.6 MHz, 14.4
MHz, 25.2 MHz and 26.0 MHz, are supported. The unique
feature of this architecture is its low spurious modulation
effect.
The use of a fractional synthesizer based on a delta sigma
modulator allows for faster lock and system set-up times,
which reduces system power consumption. The loop filter is
included on chip to minimize the external noise coupling and
to reduce the form factor applicable to the board level appli-
cation. Only one of the two RF VCOs is activated at a given
time, and each output is provided through its own output pin.
RF PLL SECTION
Frequency Selection
The divide ratio can be calculated using the following equa-
tions:
f
VCO
= {8 x RF_B + RF_A+ (RF_FN / FD)} x (f
OSC
/ R) where
(RF_A
<
RF_B) for PDC1500
f
VCO
= {4 x RF_B + RF_A+ (RF_FN / FD)} x (f
OSC
/ R) where
(RF_A
<
RF_B) for PDC800
f
VCO
: Output frequency of voltage controlled oscillator (VCO)
RF_B: Preset divide ratio of binary 4-bit programmable
counter (2
≤
RF_B
≤
15)
RF_A: Preset divide ratio of binary 3-bit swallow counter (0
≤
RF_A
≤
7 for PDC1500 and 0
≤
RF_A
≤
3 for PDC800)
RF_FN: Preset numerator of binary 10-bit modulus counter
(0
≤
RF_FN
<
FD)
FD: Preset denominator for modulus counter (FD = f
OSC
/(R
X f
CH
) where f
CH
is the channel spacing)
f
OSC
: Reference oscillator frequency
R: Internal reference oscillator frequency divider (1 for 12.6
MHz and 14.4 MHz, 2 for 25.2 MHz and 26.0 MHz)
The denominator, FD, in the above equation is dependent on
the channel spacing and reference oscillator frequency. The
channel spacing will change based on the Rx/Tx and BS
bits.
Table 6
in the R0 Register section summarizes the
values of FD.
VCO Frequency Tuning
The center frequency of the RF VCOs are determined by the
resonant frequency of the tank circuit, illustrated in
Figure 1
.
With an internal fixed bonding-wire inductor and an external
inductance, the center frequency of the VCO is given as
follows:
20068910
where C
is the total capacitance of the VCO, including
the parasitic capacitance and the nominal self-tuning capaci-
tance. Note, the external inductance consists of the PCB
traces and lumped element inductor. The output frequency
tuning range can be optimized for the specific application by
selecting the appropriate external inductance. Refer to RF2
VCO Tuning Range vs. External Inductance plot to aid in
selecting the appropriate external inductance. Care should
be taken to ensure proper frequency coverage when choos-
ing the tolerance of the lumped element inductor. For the
1500 MHz band, the internal bonding-wires provide the nec-
essary inductance to set the VCO center frequency.
In real implementation, the inductance of L
and L
can vary from its nominal value. The LMX2525 utilizes a
built-in tracking algorithm to compensate for variations up to
±
15% and tunes the VCO to the required frequency. During
the frequency acquisition period, the loop bandwidth is ex-
tended to achieve the frequency lock. After the frequency
lock, the loop bandwidth of the PLL is set to the nominal
value and the phase lock is achieved. The transition be-
tween the two operating modes is very smooth and ex-
tremely fast to meet the stringent PDC requirements for lock
time and phase noise.
POWER DOWN MODE
The LMX2525 includes the power down mode to reduce the
power consumption. The LMX2525 enters the power down
mode either by taking the CE pin LOW or by setting the
RF_PD bit in the R0 register. If the CE pin is set LOW, the
circuit is powered down regardless of the register values.
When the CE pin is HIGH, the RF_PD bit controls power to
the RF circuitry. Data can be written to the registers even
when the CE pin is set LOW. The following truth table
summarizes the power down logic.
TABLE 1. Power Down Modes
CE Pin
HIGH
HIGH
LOW
LOW
RF_PD Bit
0
1
0
1
Mode
Active
Not Active
Not Active
Not Active
20068905
FIGURE 1. External Inductor Connection
L
www.national.com
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