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參數(shù)資料
| 型號： | LMX2502 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | PLLatinum⑩ Frequency Synthesizer System with Integrated VCO |
| 中文描述： | PLLatinum⑩頻率合成系統(tǒng)的集成VCO |
| 文件頁數(shù)： | 7/18頁 |
| 文件大小： | 184K |
| 代理商： | LMX2502 |
Functional Description
GENERAL DESCRIPTION
LMX2502/12 is a highly integrated frequency synthesizer
system that generates LO signals for PCS and Cellular
CDMA applications. These devices include all the functional
blocks of a PLL, RF VCO, prescaler, RF phase detector, and
loop filter. The need for external components is limited to a
few passive elements for matching the output impedance
and bypass elements for power line stabilization.
In addition to the RF circuitry, the IC also includes IF fre-
quency dividers, and an IF phase detector to complete the IF
synthesis with the external VCO and the loop filter.
Table 1
summarizes the counter values used to generate the default
IF frequencies.
Using a low spurious fractional-N synthesizer based on a
delta sigma modulator, the circuit can support 10 kHz chan-
nel spacing for PCS and Cellular CDMA systems.
The fractional-N synthesizer enables faster lock time, which
reduces power consumption and system set-up time. Addi-
tionally, the loop filter occupies a smaller area as opposed to
the integer-N architecture. This allows the loop filter to be
embedded into the circuit, minimizing the external noise
coupling and total form factor. The delta sigma architecture
delivers very low spurious, which can be a significant prob-
lem for other PLL solutions.
The circuit also supports commonly used reference frequen-
cies of 19.20 MHz and 19.68 MHz.
FREQUENCY GENERATION
RF-PLL Section
The divide ratio can be calculated using the following equa-
tion:
LMX2502 – PCS CDMA:
f
VCO
= {8 x RF_B + RF_A + (RF_FN / f
OSC
) x 10
4
} x f
OSC
where (RF_A
<
RF_B)
LMX2512 – Cellular CDMA:
f
VCO
= {6 x RF_B + RF_A + (RF_FN / f
OSC
) x 10
4
} x f
OSC
where (RF_A
<
RF_B)
where
f
VCO
: Output frequency of voltage controlled oscillator (VCO)
RF_B: Preset divide ratio of binary 4-bit programmable
counter (2
≤
RF_B
≤
15)
RF_A: Preset divide ratio of binary 3-bit swallow counter (0
≤
RF_A
≤
7 for LMX2502 or 0
≤
RF_A
≤
5 for LMX2512)
RF_FN: Preset numerator of binary 11-bit modulus counter
(0
≤
RF_FN
<
1920 for f
= 19.20 MHz or 0
≤
RF_FN
<
1968 for f
OSC
= 19.68 MHz)
f
OSC
: Reference oscillator frequency
IF-PLL Section
f
VCO
= {16 x IF_B + IF_A} x f
OSC
/ IF_R where (IF_A
<
IF_B)
where
f
: Output frequency of the voltage controlled oscillator
(VCO)
IF_B: Preset divide ratio of the binary 9-bit programmable
counter (1
≤
IF_B
≤
511)
IF_A: Preset divide ratio of the binary 4-bit swallow counter
(0
≤
IF_A
≤
15)
f
OSC
: Reference oscillator frequency
IF_R: Preset divide ratio of the binary 9-bit programmable
reference counter (2
≤
IF_R
≤
511)
From the above equation, the LMX2502/12 generates the
fixed IF frequencies as summarized in
Table 1
.
TABLE 1. IF Frequencies
Device Type
F
VCO
(MHz)
440.76
170.67
367.20
IF_B
IF_A
f
OSC
/IF_R
(kHz)
120
120
120
LMX2502LQ1635
LMX2512LQ0967
LMX2512LQ1065
229
88
191
9
15
4
VCO FREQUENCY TUNING
The center frequency of the RF VCO is determined by the
resonant frequency of the tank circuit. This tank circuit is
implemented on-chip and requires no external inductor. The
LMX2502/12 actively tunes the tank circuit to the required
frequency with the built-in tracking algorithm.
BANDWIDTH CONTROL AND FREQUENCY LOCK
During the frequency acquisition period, the loop bandwidth
is significantly extended to achieve frequency lock. Once
frequency lock occurs, the PLL will return to a steady state
condition with the loop bandwidth set to its nominal value.
The transition between acquisition and lock modes occurs
seamlessly and extremely fast, thereby, meeting the strin-
gent requirements associated with lock time and phase
noise. Several controls (BW_DUR, BW_CRL, and BW_EN)
are used to optimize the lock time performance.
SPURIOUS REDUCTION
To improve the spurious performance of the device one of
two types of spurious reduction schemes can be selected:
A continuous optimization scheme, which tracks the en-
vironmental and voltage variations, giving the best spuri-
ous performance over changing conditions
A one time optimization scheme, which sets the internal
compensation values only when the PLL goes into a
locked state.
The spurious reduction can also be disabled, but it is recom-
mended that the continuous optimization mode be used for
normal operation.
POWER DOWN MODE
The LMX2502 and LMX2512 include a power down mode to
reduce the power consumption. The LMX2502/12 enters into
the power down mode either by taking the CE pin LOW or by
setting the power down bits in Register R1.
Table 2
summa-
rizes the power down function. If CE is set LOW, the circuit is
powered down regardless of the register values. When CE is
HIGH, the IF and RF circuitry are individually powered down
by setting the register bits.
L
www.national.com
7
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相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LMX25021635EVAL | 制造商:OC White Company 功能描述:Evaluation Board For LMX2502 PLLatinum Frequency Synthesizer |
| LMX25021635EVAL/NOPB | 功能描述:EVALUATION BOARD FOR LMX25021635 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:PLLatinum™ 標準包裝:1 系列:PCI Express® (PCIe) 主要目的:接口，收發(fā)器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要屬性:- 次要屬性:- 已供物品:板 |
| LMX2502LQ1635 | 功能描述:鎖相環(huán) - PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| LMX2502LQ1635/NOPB | 功能描述:鎖相環(huán) - PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| LMX2502LQ1635/S7001911 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Texas Instruments 功能描述: |
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