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參數(shù)資料
| 型號(hào)： | LMX2487 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 3.0 GHz - 6.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 3.0 GHz Integer PLL |
| 中文描述： | 為3.0 GHz - 6.0 GHz的高性能Δ-Σ低功耗雙PLLatinum⑩頻率合成器與整數(shù)的3.0 GHz鎖相環(huán) |
| 文件頁數(shù)： | 24/37頁 |
| 文件大?。?/td> | 856K |
| 代理商： | LMX2487 |
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Programming Description
2.0 GENERAL PROGRAMMING INFORMATION
The 24-bit data registers are loaded through a MICROWIRE Interface. These data registers are used to program the R counter,
the N counter, and the internal mode control latches. The data format of a typical 24-bit data register is shown below. The control
bits CTL [3:0] decode the register address. On the rising edge of LE, data stored in the shift register is loaded into one of the
appropriate latches (selected by address bits). Data is shifted in MSB first. Note that it is best to program the N counter last, since
doing so initializes the digital lock detector and Fastlock circuitry. Note that initialize means it resets the counters, but it does NOT
program values into these registers. The exception is when 22-bit is not being used. In this case, it is not necessary to program
the R7 register.
MSB
LSB
DATA [21:0]
CTL [3:0]
23
4
3
2
1
0
2.0.1 Register Location Truth Table
The control bits CTL [3:0] decode the internal register address. The table below shows how the control bits are mapped to the
target control register.
C3
x
0
0
0
1
1
1
1
C2
x
0
1
1
0
0
1
1
C1
x
1
0
1
0
1
0
1
C0
0
1
1
1
1
1
1
1
DATA Location
R0
R1
R2
R3
R4
R5
R6
R7
2.0.2 Control Register Content Map
Because the LMX2487 registers are complicated, they are organized into two groups, basic and advanced. The first four registers
are basic registers that contain critical information necessary for the PLL to achieve lock. The last 5 registers are for features that
optimize spur, phase noise, and lock time performance. The next page shows these registers.
L
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| LMX2487SQ | 3.0 GHz - 6.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 3.0 GHz Integer PLL |
| LMX2487SQX | 3.0 GHz - 6.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 3.0 GHz Integer PLL |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LMX2487_08 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:1.0 GHz - 6.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum? Frequency Synthesizers with 3.0 GHz Integer PLL |
| LMX2487E | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:7.5 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 3.0 GHz Integer PLL |
| LMX2487E-EVM | 功能描述:EVAL MODULE FOR LMX2487 制造商:texas instruments 系列:PLLatinum?? 零件狀態(tài):在售 類型:頻率合成器 頻率:3GHz ~ 7.5GHz 配套使用產(chǎn)品/相關(guān)產(chǎn)品:LMX2487E 所含物品:板 標(biāo)準(zhǔn)包裝:1 |
| LMX2487ESQ | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:7.5 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 3.0 GHz Integer PLL |
| LMX2487ESQ/NOPB | 功能描述:鎖相環(huán) - PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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