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參數(shù)資料
| 型號： | LMX2471 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 3.6 GHz Delta-Sigma Fractional-N PLL with 1.7 GHz Integer-N PLL |
| 中文描述： | 3.6 GHz的Δ-Σ分數(shù)N與1.7 GHz的整數(shù)N分頻PLL鎖相環(huán) |
| 文件頁數(shù)： | 16/36頁 |
| 文件大小： | 458K |
| 代理商： | LMX2471 |
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Bench Test Setups
(Continued)
SENSITIVITY MEASUREMENT PROCEDURE
20072170
Frequency Input Pin
OSCin
FinRF
FinIF
DC Blocking Capacitor
1000 pF
47 pF
100 pF
Corresponding Counter
RF_R / 2
RF_N / 2
IF_N / 2
Default Counter Value
50
500
500
MUX Value
14
15
13
OSC
0
X
X
Sensitivity is defined as the power level limits beyond which
the output of the counter being tested is off by 1 Hz or more
of its expected value. It is typically measured over frequency,
voltage, and temperature. In order to test sensitivity, the
MUX[3:0] word is programmed to the appropriate value. The
counter value is then programmed to a fixed value and a
frequency counter is set to monitor the frequency of this pin.
The expected frequency at the Ftest/LD pin should be the
signal generator frequency divided by twice the correspond-
ing counter value. The factor of two comes in because the
LMX2471 has a flip-flop which divides this frequency by two
to make the duty cycle 50% in order to make it easier to read
with the frequency counter. The frequency counter input
impedance should be set to high impedance. In order to
perform the measurement, the temperature, frequency, and
voltage is set to a fixed value and the power level of the
signal is varied. The power level at the part is assumed to be
4 dB less than the signal generator power level. This ac-
counts for 1 dB for cable losses and 3 dB for the pad. The
power level range where the frequency is correct at the
Ftest/LD pin to within 1 Hz accuracy is recorded for the
sensitivity limits. The temperature, frequency, and voltage
can be varied in order to produce a family of sensitivity
curves. Since this is an open-loop test, the charge pump is
set to TRI-STATE and the unused side of the PLL (RF or IF)
is powered down when not being tested. For this part, there
are actually four frequency input pins, although there is only
one frequency test pin (Ftest/LD). The conditions specific to
each pin are show above. The LMX2471 has a test bit that
may be useful in debugging sensitivity problems at the
FinRF pin. The location of this bit is R6[22] and should
always be set to 0 for normal operation. If this bit is set to 1,
then the sensitivity is degraded. When one suspects a sen-
sitivity problem, try setting this bit to 1 and see what hap-
pens. If the problem is unaffected, it is likely not to be a
sensitivity problem at the FinRF pin.
L
www.national.com
16
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| LMX2471 WAF | 制造商:Texas Instruments 功能描述: |
| LMX2471SLEX | 功能描述:IC PLL LP 3.6GHZ/1.7GHZ 24-CSP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應商設備封裝:* 包裝:* |
| LMX2471SLEX/NOPB | 制造商:Texas Instruments 功能描述:PLL Dual 250MHz to 3600MHz 24-Pin LAM CSP T/R |
| LMX2485 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:50 MHz - 3.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 800MHz Integer PLL |
| LMX2485_0610 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:50 MHz - 3.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 800 MHz Integer PLL |
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