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參數(shù)資料
| 型號： | LMX2433SLEX |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | PLLatinum Dual High Frequency Synthesizer for RF Personal Communications |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 3600 MHz, PQCC20 |
| 封裝： | PLASTIC, UTCSP-20 |
| 文件頁數(shù)： | 9/49頁 |
| 文件大?。?/td> | 943K |
| 代理商： | LMX2433SLEX |
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Electrical Characteristics
(Continued)
Vcc = EN = 2.5V, 40C
≤
T
A
≤
+85C, unless otherwise specified
Symbol
Parameter
Conditions
Value
Typ
Units
Min
Max
PHASE NOISE CHARACTERISTICS
L
NRF
(f)
RF Synthesizer Normalized Phase
Noise Contribution
(Note 10)
L
NIF
(f)
IF Synthesizer Normalized Phase
Noise Contribution
(Note 10)
L
RF
(f)
RF Synthesizer Single
Side Band Phase
Noise Measured
TCXO Reference Source
RF_CPG Bit = 1
IF_PD Bit = 1
TCXO Reference Source
IF_CPG Bit = 1
RF_PD Bit = 1
f
FinRF
= 2750 MHz
f = 10 kHz offset
f
COMPRF
= 1 MHz
Loop Bandwidth = 100 kHz
N
RF
= 2750
f
OSCin
= 10 MHz
v
OSCin
= 1 V
PP
RF_CPG Bit = 1
IF_PD Bit = 1
T
A
= +25
o
C
(Note 11)
f
FinRF
= 3200 MHz
f = 10 kHz offset
f
COMPRF
= 1 MHz
Loop Bandwidth = 100 kHz
N
RF
= 3200
f
OSCin
= 10 MHz
v
OSCin
= 1 V
PP
RF_CPG Bit = 1
IF_PD Bit = 1
T
A
= +25
o
C
(Note 11)
f
FinRF
= 4700 MHz
f = 10 kHz offset
f
COMPRF
= 1 MHz
Loop Bandwidth = 100 kHz
N
RF
= 4700
f
OSCin
= 10 MHz
v
OSCin
= 1 V
PP
RF_CPG Bit = 1
IF_PD Bit = 1
T
A
= +25
o
C
(Note 11)
-219.0
dBc/
Hz
-214.0
dBc/
Hz
LMX2430
-90.30
dBc/
Hz
LMX2433
-88.90
dBc/
Hz
LMX2434
-85.60
dBc/
Hz
Note 4:
Some of the values in this range are illegal divide ratios (B
<
A). To obtain continuous legal division, the Minimum Divide Ratio must be calculated. Use N
≥
P
*
(P1), where P is the value of the prescaler selected.
Note 5:
Refer to the LMX243x FinRF Sensitivity Test Setup section
Note 6:
Refer to the LMX243x Charge Pump Test Setup section
Note 7:
Refer to the Charge Pump Current Specification Definitions for details on how these measurements are made.
Note 8:
Refer to the LMX243x OSCin Sensitivity Test Setup section
Note 9:
Refer to the LMX243x Serial Data Input Timing section
Note 10:
Normalized Phase Noise Contribution is defined as : L
(f) = L(f) 20 log (N) 10 log (f
), where L(f) is defined as the single side band phase noise
measured at an offset frequency, f, in a 1 Hz bandwidth. The offset frequency, f, must be chosen sufficiently smaller than the PLL’s loop bandwidth, yet large enough
to avoid substantial phase noise contribution from the reference source. N is the value selected for the feedback divider and f
COMP
is the RF/IF phase/ frequency
detector comparison frequency.
Note 11:
The synthesizer phase noise is measured with the LMX2430TM/LMX2430SLE Evaluation boards and the HP8566B Spectrum Analyzer.
L
www.national.com
9
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LMX2433SLEX/NOPB | 功能描述:鎖相環(huán) - PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| LMX2433TM | 制造商:Texas Instruments 功能描述:PLL Frequency Synthesizer Dual 250MHz to 3600MHz 20-Pin TSSOP Rail |
| LMX2433TM/NOPB | 功能描述:鎖相環(huán) - PLL 3.6Ghz High Freq Dual Pll RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| LMX2433TMX | 功能描述:鎖相環(huán) - PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| LMX2433TMX/NOPB | 功能描述:鎖相環(huán) - PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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