參數(shù)資料
型號: LMX2372SLBX
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: XO, clock
英文描述: PLLatinum⑩ Dual Frequency Synthesizer for RF Personal Communications
中文描述: PLL FREQUENCY SYNTHESIZER, 1200 MHz, CQCC24
封裝: 3.50 X 4.50 MM, 1 MM HEIGHT, CSP-24
文件頁數(shù): 5/16頁
文件大?。?/td> 217K
代理商: LMX2372SLBX
Electrical Characteristics
(V
CC
= Vp = Vμc = 3.0V; 40C
<
T
A
<
85C except as specified). (Continued)
CHARGE PUMP
Symbol
ICP
o-source
ICP
o-sink
ICP
o-source
ICP
o-sink
ICP
o-TRI
Value
Typ
1.0
1.0
4.0
4.0
Unit
Parameter
Conditions
Min
Max
Main and Auxiliary Charge
Pump Output Current (Note 4)
VCP
o
= Vp/2,
ICP
o
_4X
= 0
VCP
o
= Vp/2,
ICP
o
_4X
= 0
VCP
o
= Vp/2,
ICP
o
_4X
= 1
VCP
o
= Vp/2,
ICP
o
_4X
= 1
0.5
VCP
o
Vp 0.5,
40C
<
T
A
<
85C
VCP
o
= Vp/2, T
A
= 25C
mA
mA
mA
mA
Charge Pump TRI-STATE
Current
CP Sink vs Source Mismatch
2.5
0.1
2.5
nA
ICP
o-sink
vs
ICP
o-source
ICP
o
vs
VCP
o
ICP
o
vs T
A
3
10
%
CP Current vs Voltage
0.5
VCP
o
Vp 0.5, T
A
= 25C
8
15
%
CP Current vs Temperature
VCP
o
= Vp/2, 40C
<
T
A
<
85C
8
%
DIGITAL INTERFACE (DATA, CLOCK, LE)
Symbol
V
IH
High-Level Input Voltage
V
IL
Low-Level Input Voltage
I
IH
High-Level Input Current
I
IL
Low-Level Input Current
V
OL
Low-Level Output Current
Value
Typ
Unit
Parameter
Conditions
Min
0.8 Vμc
Max
Vμc = 1.72V to 5.5V
Vμc = 1.72V to 5.5V
V
IH
= Vμc = 5.5V
V
IL
= 0, Vμc = 5.5V
I
OL
= 1.0 mA, V
EXT
= 1.8V (Note
5)
V
V
μA
μA
V
0.2 Vμc
1.0
1.0
0.4
1.0
1.0
0.1
MICROWIRE TIMING
Symbol
t
CS
t
CH
t
CWH
t
CWL
t
ES
Value
Typ
Unit
Parameter
Conditions
Min
50
20
50
50
Max
Data to Clock Setup Time
Data to Clock Hold Time
Clock Pulse Width High
Clock Pulse Width Low
Clock to Load Enable Setup
Time
Load Enable Pulse Width
See Data Input Timing
See Data Input Timing
See Data Input Timing
See Data Input Timing
See Data Input Timing
ns
ns
ns
ns
50
ns
t
EW
See Data Input Timing
50
ns
Note 4:
Main and Auxiliary Charge Pump magnitude are controlled by Main_ICP
o
_4X and Aux_ICP
o
_4X bits respectively.
Note 5:
Lock Detect open drain output only pulled up to V
EXT
. Typically V
EXT
= V
CC
.
1.0 Functional Description
The basic phase-lock-loop (PLL) configuration consists of a high-stability crystal reference oscillator, a frequency synthesizer
such as the National Semiconductor LMX2370/2371/2372, a voltage controlled oscillator (VCO), and a passive loop filter. The fre-
quency synthesizer includes a phase detector, a current mode charge pump, as well as programmable reference [R] and feed-
back [N] frequency dividers. The VCO frequency is established by dividing the crystal reference signal down via the R-counter to
obtain a comparison reference frequency. This reference signal (f
) is then presented to the input of a phase/frequency detector
and compared with the feedback signal (f
), which is obtained by dividing the VCO frequency down by way of the N-counter. The
phase/frequency detector’s current source output pumps charge into the loop filter, which then integrates into the VCO’s control
voltage. The function of the phase/frequency comparator is to adjust the control voltage presented to the VCO until the feedback
signal frequency and phase match that of the reference signal. When this “Phase-Locked” condition exists, the VCO frequency
will be N times that of the comparison frequency, where N is the integer divide ratio.
1.1 REFERENCE OSCILLATOR INPUT
The reference oscillator frequency for the Main and Auxiliary PLLs is provided from the external reference through the OSC
pin.
OSC
can operate up to 50 MHz with input sensitivity of 0.5 V
. The OSC
pin drives both the Main R-counter and the Auxiliary
R-counter. The input has a V
/2 input threshold that can be driven from an external CMOS or TTLlogic gate. Typically, the OSC
in
is connected to the output of a crystal oscillator.
1.2 REFERENCE DIVIDERS (R-COUNTERS)
The Main and Auxiliary R-counters are both clocked through the oscillator block in common. The maximum frequency is 50 MHz.
Both R-counters are CMOS design and 15-bit in length with programmable divider ratio from 2 to 32,767.
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