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參數(shù)資料
| 型號(hào)： | LMX2355SLB |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | PLLatinum Fractional N RF/ Integer N IF Dual Low Power Frequency Synthesizer |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 2500 MHz, QCC24 |
| 封裝： | CSP-24 |
| 文件頁數(shù)： | 14/23頁 |
| 文件大?。?/td> | 403K |
| 代理商： | LMX2355SLB |
Programming Description
(Continued)
4.1.3 15-BIT PROGRAMMABLE REFERENCE DIVIDER RATIO (R COUNTER)
(IF_R[2]–IF_R[16])
IF_R_CNTR/RF_R_CNTR
9
8
Divide
Ratio
3
4
32,767
Notes
: Divide ratio: 3 to 32,767 (Divide ratios less than 3 are prohibited).
RF_R_CNTR/IF_R_CNTR These bits select the divide ratio of the programmable reference dividers.
14
13
12
11
10
7
6
5
4
3
2
1
0
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
1
1
1
0
1
1
0
1
4.1.4 IF_CP_WORD
(IF_R[17]–IF_R[18])
CP_GAIN_8
IF_PD_POL
BIT
LOCATION
IF_R [18]
FUNCTION
IF Charge Pump
Current Gain
IF Phase Detector
Polarity
0
1
CP_GAIN_8
1X
8X
IF_PD_POL
IF_R [17]
Negative
Positive
CP_GAIN_8
is used to toggle the IF charge pump current magnitude between 1X mode (100 μA typical) and 8X mode (800 μA
typical).
IF_PD_POL
is set to one when IF VCO characteristics are positive. When IF VCO frequency decreases with increasing control
voltage IF_PD_POL should set to 0.
4.1.5 FoLD* Programming Truth Table
(IF_R[19]–IF_R[21])
FoLD
0 0 0
1 0 0
0 1 0
1 1 0
0 0 1
1 0 1
0 1 1
1 1 1
Fo/LD OUTPUT STATE
IF and RF Analog Lock Detect
IF Digital Lock Detect
RF Digital Lock Detect
IF and RF Digital Lock Detect
IF R counter
IF N counter
RF R counter
RF N counter
*FoLD - Fout/Lock Detect PROGRAMMING BITS
4.2 RF_R Register
If the Control Bits (CTL [1:0]) are 1 0, data is transferred from the 24-bit shift register into the RF_R register latch which sets the
RF PLL’s 15-bit R counter divide ratio. The divide ratio is programmed using the RF_R_CNTR word as shown in table 4.1.3. The
divide ratio must be
≥
3. The bits used to control the voltage doubler (V2_EN) and RF Charge Pump (RF_CP_WORD) are
detailed in 4.2.2.
MSB
DLL_MODE
23
LSB
0
0
V2_EN
RF_CP_WORD [4:0]
22 21
RF_R_CNTR [14:0]
17 16
1
2 1
L
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