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參數(shù)資料
| 型號： | LMX2352TM |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | CAP,CER,DISC,RAD,100PF,10%,1KV |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 1200 MHz, PDSO24 |
| 封裝： | PLASTIC, TSSOP-24 |
| 文件頁數(shù)： | 16/20頁 |
| 文件大?。?/td> | 378K |
| 代理商： | LMX2352TM |
Programming Description
(Continued)
Synchronous Power down Mode
One of the PLL loops can be synchronously powered down
by first setting the power down mode bit HIGH (IF_N[21] = 1)
and then asserting its power down bit (IF_N[22] or RF_N[22]
= 1). The power down function is gated by the charge pump.
Once the power down bit is loaded, the part will go into
power down mode upon the completion of a charge pump
pulse event.
Asynchronous Power down Mode
One of the PLL loops can be asynchronously powered down
by first setting the power down mode bit LOW (IF_N[21] = 0)
and then asserting its power down bit (IF_N[22] or RF_N[22]
= 1). The power down function is NOT gated by the charge
pump. Once the power down bit is loaded, the part will go
into power down mode immediately.
Prescaler select
is used to set the RF prescaler. The
LMX2350 is capable of operating from 500 MHz to 1.2 GHz
with the 16/17 prescaler, and 1.2 GHz to 2.5 GHz with the
32/33 prescaler selection. The LMX2352 is capable of oper-
ating from 250 MHz to 500 MHz with the 8/9 prescaler, and
500MHz to 1.2GHz with 16/17 prescaler selection.
4.2.2 5-BIT RF SWALLOW COUNTER DIVIDE RATIO
(RF A COUNTER)
(RF_N[6]-[10])
Swallow Count
(A)
0
1
-
31
Note:
Swallow Counter Value LMX2350: 0 to 31; LMX2352: 0 to 15
RF_NB_CNTR
≥
RF_NA_CNTR + 2
RF_NA_CNTR
2
0
0
-
1
4
0
0
-
1
3
0
0
-
1
1
0
0
-
1
0
0
1
-
1
4.2.3 10-BIT RF PROGRAMMABLE COUNTER DIVIDE
RATIO (RF B COUNTER)
(RF_N[11]-[20])
RF_NB_CNTR
7
0
0
-
1
Divide Ratio
3
4
-
1,023
Note:
Divide ratio: 3 to 1023 (Divide ratios less than 3 are prohibited)
RF_NB_CNTR
≥
RF_NA_CNTR + 2
9
0
0
-
1
8
0
0
-
1
6
0
0
-
1
5
0
0
-
1
4
0
0
-
1
3
0
0
-
1
2
0
1
-
1
1
1
0
-
1
0
1
0
-
1
4.2.4 FRACTIONAL MODULUS ACCUMULATOR (FRAC_CNTR)
(RF_N[2]-[5])
Fractional Ratio (F)
Modulus 15
0
1/15
2/15
-
14/15
N/A
FRAC_CNTR
Modulus 16
0
1/16
2/16
-
14/16
15/16
RF_N[5]
0
0
0
-
1
1
RF_N[4]
0
0
0
-
1
1
RF_N[3]
0
0
1
-
1
1
RF_N[2]
0
1
0
-
0
1
4.3 PULSE SWALLOW FUNCTION
fvco = [N + F] x [fosc / R ]
N = (P x B) + A
F:
Fractional ratio (contents of FRAC_CNTR divided by
the fractional modulus)
fvco: Output frequency of external voltage controlled oscil-
lator (VCO)
B:
Preset divide ratio of binary 10-bit programmable
counter
A:
Preset value of binary 4 or 5-bit swallow counter (0
≤
A
≤
31 {RF} , 0
≤
A
≤
15 {IF} , A+2
≤
B {RF}, A
≤
B {IF})
fosc: Output frequency of the external reference frequency
oscillator
R:
Preset divide ratio of binary 15-bit programmable ref-
erence counter (3 to 16383)
P:
Preset
modulus
of
(LMX2350:RF P=16 or 32, IF P=8)
(LMX2352:RF P=8 or 16, IF P=8)
dual
modulus
prescaler
4.4 CMOS (Programmable CMOS outputs)
(IF_N[17]-[20])
MSB
FastLock
LSB
TEST
OUT_1
OUT_0
Note:
Test bit is reserved and should be set to zero for normal usage.
www.national.com
16
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