參數(shù)資料
型號(hào)： LMX2335MX
英文描述： Serial-Input Frequency Synthesizer
中文描述： 串行輸入頻率合成器
文件頁(yè)數(shù)： 16/19頁(yè)
文件大?。?/td> 362K
代理商： LMX2335MX
1.7 Application Information
(Continued)
1.7.6 N COUNTER
The calculated value of N, and the value of P are now used to determine the values of A and B where A and B are both integer
values:
N = P
*
B + A
where B is the divisor and A is the remainder. Therefore:
B = div (N/P)
and
A = N (B
*
P)
For this example, B and A are calculated as follows:
B = div (4750/32) = 148 = 0000010010100
and
A = 4750 (148
*
32) = 14 = 01110
To load the N counter with these values, the programming bit stream would be as follows. The first bit, the GO bit, (MSB) N[19]
is used for FastLock operation and will be discussed in the F Latch section. The next 13 bits, (N[18]–N[6]) shifted in, are the B
counter value, 0000010010100
*
. Bits N[5]–N[1] are the A counter and are 01110
in this example. The final two bits (the control
bits) are 1,0 identifying the N counter. In programming the N counter, the value of B must be greater than or equal to A, and the
value of B must be greater than or equal to 3.
Note:
*
In programming the counter, data is shifted in MSB first.
1.7.7 R COUNTER
Programming the R counter is done by shifting in the binary value of R calculated previously (50
= 110010
). The first bit shifted
in is R[19] the LD precision bit. The next 4 bits (R[18]–R[15]) shifted in, are used for testing and should always be loaded with
zeros. The R[14]–R[1] bits are used to program the reference divider ratio and should be 00000000110010
for this example. The
final two bits, C[1] and C[2] denote the R counter and should be 0, 0. The resulting bit stream looks as follows:
1.7.8 F LATCH
To program the device for any of the FastLock modes, C[1] = 0 and C[2] = 1 which direct data to the F latch. The Section 1.3
FUNCTION AND INITIALIZATION LATCH section discusses the 4 modes of FastLock operation. The user must first determine
which FastLock mode will be used. When using any of the FastLock modes, the programmer needs to experimentally determine
the length of time to stay in high gain mode. This is done by looking at the transient response and determining the time at which
the device has settled to within the appropriate frequency tolerance. FastLock mode should be terminated just prior to “l(fā)ock” to
place the switching phase glitch within the transient settling time. The counter reset mode (F[1] bit) holds both the N and R
counters at load point when F[1] = HIGH. Upon setting F[1] = LOW, the N and R counters will resume counting in close phase
alignment. Other functions of the F latch such as FoLD output control, Phase detector polarity, and charge pump TRI-STATE are
defined in the 1.3 FUNCTION AND INITIALIZATION LATCH section also.
DS100127-14
DS100127-16
L
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